Multicore microprocessors and embedded multicore SOCs have very different needs

Update: Cadence Completes Acquisition of Tensilica (Apr 24, 2013)

By Steve Leibson, Tensilica, Inc.
Jul 18 2007, Embedded.com

The term "multicore" seems to be getting a lot of use these days. For example, there's an industry association dedicated to the idea and the IEEE Computer Society's Computer [1,2] magazine recently devoted two cover stories to the concept. Like the poem about the blind men and the elephant [3], the term appears to mean many different things to different people depending on the context.

When used to describe PC-class microprocessors, the phrase nearly always refers to on-chip arrays of identical, single-ISA (instruction-set architecture) processors that handle processing loads using homogeneous or symmetric multiprocessing (SMP) and shared memory.

For SOC designs, the term may refer to shared-memory SMP architectures but it can also mean heterogeneous (single-ISA or multiple-ISA), single-chip, asymmetric multiprocessing (AMP) designs, with or without shared memory. Therefore, whenever you see a reference to a multicore chip or design, you need to dig deeper to clarify how the term is being used.

SMP and AMP approaches with and without shared memory can be used to solve processing problems that are beyond the capabilities of an individual microprocessor. Multicore PC and server microprocessors based on the x86 architecture started to appear after Intel and AMD hit the clock-rate wall and could no longer increase single-core-processor clock rates the way they did throughout the 1990s.

The maximum clock rates of these processors approached 4 GHz, at the cost of excessive power consumption, heat dissipation, and electromigration-related reliability concerns.

The path to further increases in processor performance through increased clock rates appeared to be blocked. An alternate path involved putting two and then four identical processor cores (and later eight and probably 16 processor cores) on a chip with both cores running at a lower clock rate to reduce power consumption and heat dissipation.

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