Using HW emulators to get HW/SW right the first time on the Sun UltraSPARC T1 processor

By Jai Kumar, Sun Microsystems    
August 08, 2007 -- pldesignline.com

Overview

In today's highly competitive marketplace with its associated time-to-market pressures, it is now more important than ever to get your product right the first time. And this principle of designing effectively from the start was no different for the Sun UltraSPARC T1 processor with CoolThreads technology. One of the highest throughput and most eco-responsible processors available, the Sun UltraSPARC T1 processor features a unique multi-core, multithreaded design that supports up to 32 simultaneous threads, posing new verification challenges. We embraced this challenge by enhancing verification efficiency and by adapting aggressive changes in verification methodology and state-of-the-art verification tools and technologies.

The Sun UltraSPARC T1 processor design – along with its system-level test bench – is unusually large (around 35+ million gates). This posed a capacity and performance issue for our verification tools and made it difficult to quickly run the required number of verification cycles needed to attain high verification confidence and tape-out the design. In fact, our need to run verification cycles in a timely fashion forced us to seek a new set of tools and develop a rich, multi-vendor tool set that has become the key ingredient in our block, chip, and system level functional verification methodologies.

By combining best-of-breed simulation, formal verification, and emulation tools from internal and external sources, we have successfully solved numerous verification challenges such as design size and complexity. We've deployed acceleration and emulation technologies allowing us to perform system integration and functional verification tasks that are typically completed after the arrival of silicon prior to design tape-out.

Introduction

Designing your product right from the start involves many different aspects of design, development, and manufacturing. This article addresses only the functional verification aspect of the design development process. The functional verification of a systems-level environment involves not only the verification of hardware (HW) – including processor architecture, RTL design, and DFT – but also of software (SW) including the firmware, operating system and various device drivers. Traditionally, the development tasks or phases of a systems-level design verification are completed in sequential order. This process is not only logical, but it is also reduces risks in product development.

Due to market forces, however, such as the need to decrease cost and shorten time-to-market, a logical, sequential process is not always possible. In our current business environment, we try to parallelize as many of those phases as we can to shorten the product development cycle and maintain our competitiveness in the marketplace. Market factors and a new testing process compound the complexity of system-level functional verification and force us to investigate new solutions.

This paper describes the methodology, tools, and techniques that were used to address and resolve Sun's system-level verification challenges and deliver a high quality product in a timely manner. Simulation, Emulation and Formal verification tools were deployed at various levels of design abstraction; however, emulation played a key role in ensuring system level verification that spanned both HW and SW verification.

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