Characterizing Nanometer CMOS PLLs, Sigma-Delta ADCs and AGCs

By Yiqun Lin, Silicon Laboratories
May 13, 2008 -- edadesignline.com

A critical limitation in taping out high-performance mixed-signal ICs is the characterization of complex analog/RF blocks such as phase locked loops (PLLs) and analog-to-digital converters (ADCs). As we strive to extend our leadership in the semiconductor business, we are always looking for ways to accelerate our analog/RF verification flow without increasing the risk of silicon that does not meet specifications. We have three key requirements for analog/RF simulators: accuracy, performance and capacity. This article describes the application of Analog FastSPICETM (AFS) from Berkeley Design Automation (BDA) to the pre-tapeout characterization of a nanometer-scale CMOS PLL, sigma-delta ADC and an automatic gain control (AGC) circuit. These production circuits are representative of our most complex analog/RF blocks. In each case, we compared the results of our "golden" traditional SPICE simulator with those of AFS. Despite our initial skepticism, AFS met or exceeded BDA's claims on all counts " identical waveforms, 5 -10x higher performance and sufficiently higher capacity to handle our most complex applications. We now rely on AFS to verify our most difficult complex blocks and even to run our full-circuit simulations.

Click here to read more ...