Software-to-silicon verification @ 45 nm and beyond

Tom Borgstrom and Badri Gopalan, Synopsys
EE Times (07/13/2009 12:01 AM EDT)
 
Chip and system developers once considered verification as a secondary activity following the main challenge of design, with the "Designer" playing the central role in a design's success. This notion is firmly turned on its head today, as verification is the biggest component of chip hardware development budgets, schedules, staffing and risk.

With verification complexity growing faster than Moore's Law, compounded by increasing mixed-signal content and advanced low-power design techniques, the importance of verification in the chip hardware development process is certain to increase. In fact, venture capitalists have started focusing on verification costs as a factor in determining which chip startups to fund. Similarly, embedded software used to be a minor or nonexistent deliverable for typical semiconductor devices. At 45 nm and beyond, software accounts for a full 60 percent of total chip-development cost, with major implications on how chips and systems are verified. It is no surprise, then, that the International Technology Roadmap for Semiconductors (ITRS) predicts that, "Without major breakthroughs, verification will be a non-scalable, show-stopping barrier to further progress in the semiconductor industry."

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