Clock sources with integrated power supply noise rejection simplify power supply design in FPGA-based systems

By Juan Conchas, Silicon Laboratories Inc.
pldesignline.com (October 06, 2009)

By their nature, FPGAs are power hungry devices with complex power delivery requirements and multiple voltage rails. A single chip commonly consumes multiple watts of power while operating from 1.8 V, 2.5 V and 3.3 V rails. Activating high speed on-chip SERDES can increase power consumption by several watts and complicate the power delivery strategy. When FPGA power consumption increases, performance requirements on sensitive analog and mixed-signal subsystems also increase. Chief among these are the clocking subsystems that provide low jitter timing references for the FPGA and other board-level components.

Power hungry systems cannot be free of power supply noise. In general, system designers try to use low noise linear power supplies whenever possible. However, excessive power dissipation usually prevents the use of linear regulators. When using a linear device, regulating from 3.3 V input to 1.8 V output is only 54% efficient regardless of the load current. Low conversion efficiency burns power in the regulator instead of the load and makes linear devices unsuitable for many high performance applications.

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