SoCs: Supporting Socketization -> Socketization gets to core of plug-and-play IP

Socketization gets to core of plug-and-play IP

Socketization gets to core of plug-and-play IP
By Michael Santarini, EE Times
January 3, 2000 (3:08 p.m. EST)
URL: http://www.eetimes.com/story/OEG20000103S0038

Five years ago, the answer to how to fill the millions of gates afforded by emerging process geometries sounded so simple it could be framed with five little words: plug-and-play intellectual property. People thought design groups could simply connect random blocks of Verilog, VHDL and GDSII together to create a system-on-chip (SoC) for each product generation. Of course, that was easier said than done.

With the first wave of ill-equipped third-party intellectual-property (IP) companies having been largely wiped out, and in the wake of numerous hard-learned design-in lessons, it appears that plug-and-play is finally becoming a reality and that SoC design is moving into the mainstream.

Fueled by the work of the Virtual Socket Interface Alliance standards body, companies have introduced design architectures that promise to facilitate the plug-and-play of IP cores. EDA vendors and semiconductor companies have produced tools and reuse methodology manuals that bring the wisdom of the SoC pioneers to the mainstream. And chip and system companies have established strict internal design-for-reuse guidelines, hoping those practices will become commonplace.

Dataquest's Gary Smith cites the four basics of socketization: Make sure the design doesn't violate your design rules, modularize the testbench, make the design usable by multiple EDA tools and wrap it for inclusion in a design database

Indeed, the design community has gained a more realistic understanding of what it takes to make an IP block reusable and primed for connection in a plug-and-play environment. But perhaps the single biggest lesson of the past five years is what it really takes to turn a design into a core.

Th at process is widely called socketization. Gary Smith, chief EDA analyst at Dataquest Inc. (San Jose, Calif.) describes the basics: "First, a quality-assurance process ensures the design hasn't violated any of your design rules. Second is to ensure that the testbench is modularized for ease of use. In addition, it must produce various views so that a design may be used by various EDA tools. [Finally], it must wrap the design so that it may be used with a platform or in a design database."

In this "Focus" section, we hear from EDA vendors and designers at the forefront of defining socketization. VSIA's Mark Birnbaum outlines what is needed to turn an IP block into a "virtual component." Jeff Jussel, director of Mentor Graphics' Consulting Division, describes its QuickUse environment. Aparna Dey and Grant Martin, senior technical architects at Cadence Design Systems, offer a primer on detailing integration-driven reuse approaches to SoC design. Warren Savage, engineering director for Synopsys' design-r euse business unit, explains a method for creating socketized cores.

Sonics Inc.' senior vice president for product development, Geert Rosseel, looks at its new plug-and-play environment and offers a contrarian view of socketization. Marines Puig-Medina, member of the technical staff at Tensilica, describes how that company packaged its microprocessor core. Finally, Michael T. Y. McNamara, senior VP of technology at Verisity, and LSI Logic design engineer Jeffrey J. Holm discuss the importance of a verification environment and integration strategies.