On-chip test generators said to be key to cost control

On-chip test generators said to be key to cost control
By Laurie Sullivan, EBN
March 12, 2002 (7:54 p.m. EST)
URL: http://www.eetimes.com/story/OEG20020312S0064

SCOTTSDALE, Ariz.- The spiraling cost of testing will force chip designers to include on-chip test generators, said Walden Rhines, CEO of Mentor Graphics, during his keynote address at the Semico Summit 2002 here.

Engineers that design large systems on chip can spend millions to verify the interface between a digital signal processing core and CPU core because the variables are infinite, he said.

The semiconductor industry until ten years ago spent two-thirds of its time creating the design. Today they spend two-third of its time running simulations to verify the design will work. With a traditional simulator, Rhine said, it takes about a week to test a leading edge processor box for bugs.

"Recent improvements in cost of compressed scan-based testing can help customers improve quality tests and achieve 90% reduction in tester memory," Rhines said. "We are going to have to put the test generators on the chip because we're not going to be a ble to afford the test generators for all these patterns."

Some companies spend 50% on testing. A company that does complex microprocessors testing, Rhines said, can save up to $1 billion per year by doing compressed scans. The embedded testing is not expected to increase time-to-market.

"Continued design productivity growth will force the adoption of platform-based designs both in field programmable and ASIC," he said. "It will also lead to the adoption of hardware acceleration and emulation to verify complex systems. Major cost reductions will occur in the next year or two instead of being stretched out over the whole cycle."

The cost per tester reached $7 million in 2001, with expectations it will climb to roughly $9 million by 2003, according to Semico Research Corp., Phoenix.