By Synopsys
Security is a first-order design requirement for processor-based systems. Processor designers implement security functionality directly into the hardware itself to protect the system at its most fundamental layer. System integrators that use processor IP such as Synopsys’ DesignWare® ARC® processors must ensure that they configure and manage the protection and security features correctly, and that they do not introduce vulnerabilities. Evaluating the security of complex, highly combined hardware-software systems and ensuring these systems are free from vulnerabilities is hard. In this white paper, we show how Tortuga Logic’s Radix-S security verification platform with Synopsys’ ARC Processor IP offer a powerful solution for this complex problem. We demonstrate the combined hardware-software security verification by creating an example system comprised of the ARC processor IP and vulnerable software that configures the memory protection unit incorrectly. With the additional capabilities provided by Radix-S, we quickly identify the flaw using pre-existing functional verification infrastructure. Furthermore, we show how system integrators can verify the security of protected debug logic with this technology.
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