Optimize SoC Design with a Network-on-Chip Strategy

By Andy Nightingale, Arteris

Utilizing physically aware interconnect IP from trusted third-party vendors can reduce design time and increase productivity.

Today’s system-on-chip (SoC) devices can contain hundreds of millions to over a hundred billion transistors, depending on the application. The only way to create designs of this complexity is to employ large numbers of functional blocks called intellectual-property (IP) blocks or IPs.

Many of these blocks embody well-known and standard functions, such as processor cores, communication cores (Ethernet, USB, I²C, SPI, etc.) and peripheral processes. Rather than spend valuable time and resources re-implementing these functions from scratch, SoC design teams acquire these IPs from respected third-party vendors.

Access to robust, tested, and proven IP speeds up the development process and reduces risk. Using third-party IP for common functions frees the SoC design team to focus on their own “secret sauce” IP blocks, which will differentiate their SoC from competitive offerings.

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