EUV Will Not be Ready For 14nm, says Imec President..

 “I believe the time to decide lithography options for 14nm is basically now, and it’s clear EUV is not ready for the challenge,” said van den Hove.

One option at 14nm is triple patterning, but this would increase wafer cost by 90% compared to 28nm, said van den Hove.

The increased cost if EUV were used would only be 60%, but van den Hove said that EUV will not be available until 2014 and, even then, will only be capable of limited commercial use.

Triple patterning is so tricky that design rules will have to be relaxed to achieve satisfactory yield. “It is likely some design rules at 14 nm will have to be relaxed somewhat,” said van den Hove.

“For the last 40 years, a 50% area reduction with doubling of the transistor density every 14 months has been the engine of the semiconductor industry,” said van den Hove, “EUV pre-production tools are capable of patterning at 16nm half pitch with one single exposure, and allows an overlay of 2nm. EUV lithography, however, comes at the expense of new equipment and process challenges, and much work is currently ongoing to make the tool and the source power production ready.”

The source power is the main problem. 20-30W is being achieved; 100W is needed; 125-250W is required for a tool able to handle 60-120 wafers an hour.

As flash runs into scaling problems, van den Hove believes in the potential of resistive RAM. “Below 10nm half pitch, the flash memory market might be revolutionised by the introduction of resistive RAM, which is a promising concept because of its high speed, superior scalability and compatibility with CMOS technology, and improved reliability as compared to scaled NAND flash,” said van den Hove.