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“Intel may have technological reasons for adopting this shape but by doing so you reduce performance by 12-15%,” Asenov tells me.
With IBM licensing a potentially higher performing finfet design to UMC, Asenov’s findings raise the prospect of Intel having to go back to the drawing board and re-engineer its finfets. That would set Intel’s product and process technology plans back by a year or more.
In a paper on the GSS website, Asenov points out that, while Intel bulk FinFETs have 12%-15% less performance than equivalent rectangular bulk FinFET, compared to rectangular ‘bulk’ FinFETs, rectangular SOI FinFETs have either 5% higher drive current at equivalent threshold voltage and leakage, or 2.5 times less leakage at equivalent on current.
“Bearing in mind that it is easier to make rectangular SOI FinFETs than rectangular bulk FinFETs, moving from triangular Intel bulk FinFETs to rectangular SOI FinFETs can deliver approximately 20% performance improvement,” says Asenov.
Asked why he thinks Intel has adopted this disadvantageous shape, Asenov replies: “We have very little solid knowledge. Maybe there’s a technological reason associated with the deposition of HK gate dielectric over vertical walls.”
“IBM can make nice rectangular shaped vertical walls,” adds Asenov.
This could be a problem for Intel because IBM has licensed its technology to UMC, the No.2 foundry.
Meanwhile Gobalfoundries, the No.3 foundry, is preparing SOI technology.
“There has never been a time in my life, and I’ve been in this business for 35 years, when it’s been so exciting and so complicated,” says Asenov, “companies will have to decide on the different technologies and these will be very expensive decisions. It will also mean very difficult decisions for the fabless companies.”
If Intel has to go back and re-engineer its finfets, it will lose the process technology advantage it currently enjoys. If it decides not to to re-engineer its finfets, Intel could find its process technology produces ICs which under-perform ICs made on the finfet processes which will be deployed at the key foundries.
David, We agree that the triangular fin is a manufacturing compromise. My point is that having these ‘compromised’ FinFET in high volume production will drive enhancements to the process – as well as allowing them to trial more aggressively rectangular solutions on real products. With all the test, characterisation and reliability infrastructure that this gives.
And as previously mentioned it gives them a great ‘test bed’ for refining the changes to their design styles to cope with a integer choice on transistor weff. Let’s not be naive in thinking that Intel are doing this ‘for fun’.
Although I am worried about Intel’s leadership in process development and the potential monopolistic impact on the industry not sure triangular FinFETs will kill them. Instead we should see this as further evidence of why they are in the lead i.e. an ability to make big calls and engineer ways around problems as they occur. In much the same way TSMC has confronted its 28nm yield issues…
It is demonstrably true that the triangular fin is a manufacturing compromise, Henry, but that doesn’t mean it’s uninteresting to discuss the Whys and Wherefores of the triangular fin. Intel hasn’t told us Why the fin is triangular, but Prof Asenov tells us the Wherefore – i.e 15% performance degradation. Everyone says: ‘Isn’t Intel clever to make finfets?’ But a better question is: ‘What effect is Intel’s finfet process having on the performance of the ICs made on the process?’ If the manufacturing compromises mean the answer is ‘Not much’, then it means other companies have a chance to catch up. I would suggest that’s a good thing.
I agree with WW. Intel must be chuckling away about all the press they are getting on what is in effect an engineering compromise to allow them to get into high volume manufacture using FinFET technology. Volume drives ‘cycles of learning’, which drives process yield and parametric control. Also one of the biggest problem with any new process introduction into high volume is refining the sensitive analog cells/IP that differentiate modern designs – with the integer multiple drive strength restrictions of the FinFET process think what a head-start Intel is giving it’s analog/RF design teams by having a manufacturing process to ‘play’ with! Perfect example of a ‘bird in the hand V bush…’ and makes their priority of 450mm (long term cost reduction) completely understandable.
That’s right Mike, the same lot who invented the HDD, DRAM, SiGe, the scanning tunelling microscope and have five Nobel Laureates among their employees. BTW: the quote about IBM’s ‘nice rectangular walls’ came from Prof Asenov, but the bit about ‘This could be a problem for Intel becasue IBM has licensed its technology to UMC’ were my words.
“IBM can make nice rectangular shaped vertical walls,” adds Asenov.
This could be a problem for Intel because IBM has licensed its technology to UMC, the No.2 foundry.”
This wouldn’t be the same IBM that gave us the gate-first fiasco would it ?
In any case a 14nm (most probably less-)triangular TriGate will still out-perform a 20nm rectangular FinFet in speed, power and cost, even if the yields were even of the same order, which they won’t be.
@ww : there is an EC programme called SOI450 to produce 450mm SOI wafers, and the company processing those wafers for Soitec is … Intel.
Azzouz Nezar writes: I believe Dr. Asenov is on the right track. I believe there is some liability issue that will hunt Intel soon like in the Flash and Xscale. As for why the finfet shapes changed, from the comment on your blog, the authors are on the right track. I believe integration challenges of the rectangular fin were overlooked. I suspect the NMOS transistor fin is the culprit. Despite the metal gate, the work function value is not perfect and needs some doping level in the fin. “Boron” may be used in the NMOS fin, and some of it get consumed or outdiffused from the surface which lead to leakage. Compensating this boron loss on the side wall is not easy. I susepct the issues got obvious when they started ramping-up manufacturing! So they choose to taper the wall (in addition to tilting implants). Dopant fluctuation may also add to the problem considering the low dose and well controlled doping density needed at the surface of the fin. The other thing, that I suspected but I have been out from the industry for a while to confirm, is perhaps the conformity of the high K dielectric film covering the fins. Coverage on the sidewall of finfet may have been poor in rectangular shapes (for Intel case). Intel may tapered this finfet so to improve conformity! As for the shape of the fins (now triangular) a close look suggest no guarantee to scale down further. Next shrink may lead to lift-off of hard mask. So they need to back off on the lateral etch of silicon that made fin triangular.
The performance difference between bulk rectangular finfets and bulk triangular finfets is 12-15%, WW, not 5%.
This story keeps getting dredged up. The answer is right there in the article — it’s easier to make rectangular finfets on SOI wafers than on bulk wafers. Intel’s not planning on going back to the drawing board — by deploying bulk finfets they avoid the added cost and complexity of SOI wafers while generating the engineering and manufacturing knowledge required to build such complex structures at advanced process nodes. They may also be testing out the sloped finfets with an eye towards 450mm manufacturing — if they can maximize yield of high performance parts off a 450mm wafer, Intel should have a tremendous cost advantage over any competitors still on 300mm (Are 450mm SOI wafers even available?), even if competitor’s parts are a little faster.
The sloping walls of the fins are likely easier to manufacture with high yield than fully rectangular finfets — there’s no sense spending an extra year developing a rectangular fin process when you can start out with a looser process that gets you a marketable (or at least testable) product that’s only 5% off of the performance of its (more expensive) competitor?
Expect Intel to tighten up the process over the next year or so. In the meantime they’ll be developing an actual chip, instead of an individual transistor.