The Xilinx-Altera ding-dong is one of the staple axes of the semiconductor industry and often the slings and arrows of their respective fortunes depend on each company’s response to a new process node.

Altera performed well on 40nm while Xilinx screwed up.

On 28nm, Xilinx got there first and is determined to extend its market share lead as a result.

On 20nm, Altera is making a precocious play, announcing the launch of a  product for next year which will have 60% better ‘total’ power saving (i.e. active + static power saving) than the 28nm range.

Asked how that could be achieved on a process which is expected to be power hungry, Vince Hu, vp for product and corporate marketing at Altera, tell me: “more than half of that comes from design.”

The TSMC 20nm , which both Altera and Xilinx will use, is expected to be power hungry, according to Professor Asen Asenov of Glasgow University who is CEO of Gold Standard Simulations.

“My understanding is that 20nm will be a power hungry node,” says Asenov, “only the big players with high performance products will consider it. The rest will stay with 28nm as long as possible or until better finfet options become available.”

Altera’s intention is to launch 20nm product next year with volume production in 2014. However it is also working on product which will use TSMC’s 16nm finfet process.

At the same time it is, so Altera’s CTO, Misha Burich, tells me keeping a watchful eye on FD-SOI as a possible way to go.