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Globalfoundries intends to have 14nm finfet in volume manufacturing in 2014, the same timescale as Intel has for introducing 14nm finfet manufacturing.
In fact, GF’s 14nm process may use smaller transistors than Intel’s, said Chian because “Intel’s terminology doesn’t typically correlate with the terminology used by the foundry industry. For instance Intel’s 22nm in terms of the back-end metallisation is similar to the foundry industry’s 28nm. The design rules and pitch for Intel’s 22nm are very similar to those for foundries’ 28nm processes.”
On the Intel 22nm process the drawn gate length is actually 26nm.
GF’s 14nm process delivers a number of benefits over 20nm. “One benefit is that it reduces development time because people can easily migrate from 20nm to 14nm,” said Chian, “customers can use the same GDSII and swap the transistors.” GF calls it ‘fin-friendly migration.’
Fin-friendly migration benefits from the characteristic of GF’s 14nm process that it retains the 20nm interconnect while moving to 14nm transistors.
Other benefits of GF’s 14nm are that it will deliver 20-55% higher performance than 20nm depending on the operating voltage, or that it can deliver 40-60% better battery life with the same performance.
The GF 14nm technology uses rectangular-shaped fins. That could change when it moves into volue manufacturing when the exigencies of real-world production require compromises, but GF’s current expectation is that the rectangular shape will survive into manufacturing. Intel has had to go to a triangular-shaped fin which reduces the performance and the power-saving benfits of finfets.
At the front of the GF 14nm finfet node will be mobile SOCs. GF has been working with ARM since 2009 to optimise its processes for ARM-based SOCs. 14nm will be the first process at which Intel will put mobile SOCs to the front of the node.
By moving to 14nm finfet while keeping 20nm interconnect, GF has brought forward the intorduction of its 14nm process by one year.
Next year GF starts production on 20nm. GF’s 20nm SRAM, and various customer test chips on 20nm, are yielding “very well”, said Chian.
Maybe the latter, Scunnerous, because Chenming Hu said he thought others would follow the GF-IBM approach of 14nm fin /22nm interconnect.
With GF’s history of near-zero initial gains from node shrinks, dating back to AMD days even, this all seems awfully optimistic to me. Even if bulk CMOS changes the picture there, vs. SOI, it was my understanding that Intel, TSMC and Samsung had cornered the early tools for 14nm from ASML. Or is there a hint here that the GF-IBM alliance has cooked up a different, novel approach to 14nm in Malta, NY?
So the ‘performance’ answer relates to reduced leakage, Anonymous?
http://www.eetimes.com/design/eda-design/4398011/FinFET-structure-design-and-variability-analysis-enabled-by-TCAD-?pageNumber=1&Ecosystem=eda-design
Synopsys show how rectangular fins have better current drive but tapered fins have lower leakage.
Yes indeed, Anonymous, even those old dinosaurs the Wall St analysts are urging Intel to change – but one wonders if it can. The management have spent a decade trying to persuade its engineers to make low-power chips and have patently failed.
The lizard titans have to fight the nimbler rodents eating away on their profits in an ever increasing pace and at the same time it’s getting colder, cloudier and more barren outside.
What did evolution teach us again?
Adapt or perish.