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In October I spoke to three CEOs aiming to to license FPGA cores.
Although conceding that embedded FPGA is an idea whose time has one, each of them denied that they were influenced by the others’ initiatives or by the Intel/Altera deal.
Mind you John Daane, CEO of Altera before it was bagged up by Intel, has been preaching the wonders of FPGA hardware acceleration for some years.
The three CEOs now bringing eFPGA to the general SoC designer market are Robert Blake of Achronix, Brian Faith of QuickLogic and Geoff Tate of Flex Logix.
There is a technical explanation for why embedded FPGA has suddenly become the flavour du jour: “In the past it was too expensive,” says Blake, “it took too much silicon area on the die to implement a useful function. Now, with 16nm, all of a sudden these things make sense.”
For Achronix and QuickLogic it’s a question of tacking on a licensing business to their stand-alone FPGA businesses, for Flex Logix, a two and a half year-old start-up backed by $7.4 million of venture money, licensing is the entirety of what they do.
Two of the trio are TSMC customers and one is going for GloFo FD-SOI.
Achronix’ Speedcore FPGA cores are being fabbed on TSMC’s 16FF+ process and will be migrated to TSMC’s 7nm process in H1 2017.
Flex Logic is the other TSMC house and an SoC design using its core is being taped out on TSMC’s 16nm process.
The exception is QuickLogic which is going to GloFo – initially for 65nm and 40nm processes but, as from next year, moving to GLoFo’s 22nm FD-SOI process.
The choice of GloFo FD-SOI is, says Faith, “because it’s low power and a lot less complex than finfet.” Scalability is assured, he says, down to 12nm.
Flex Logic has developed a technology to join cores together. 49 cores, each containing 2,500 LUTs, can be stitched together to implement a 100,000 LUT block on a 16nm SoC design.
So competition is coming to re-configurable SoCs, and FPGA hardware acceleration is becoming a democratised capability with multiple sources and a variety of approaches and costs.
