CI1 : Custom Global Clock Tree Distribution: A Case for Automation Using SKILL Scripting Language
Mahesh Am, AMD
Prateek Mishra, AMD
Animesh Jain, AMD
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CI2 : IC Technology Trends and Challenges with Unified Virtuoso Technology-Based Solutions for Advanced Nodes
Sandeep Torgal, GLOBALFOUNDRIES
Vinay AB, GLOBALFOUNDRIES
Pratik Korde, Cadence
Jonathan Fales, Cadence
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CI3 : A Novel I/O Pad Cluster Development Methodology Using Cadence Design Framework II (DFII) Library Builder
Rajesh Mangalore Anand, AMD
Aniket Waghide, AMD
Girish A S, AMD
Jagadeesh AS, AMD
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CI4 : Increased Productivity Solution for Full Custom Layout
Rajeev Singh, STMicroelectronics
Atul Bhargava, STMicroelectronics
Monika Lilani, STMicroelectronics
Shubham Gupta, STMicroelectronics
Komal Arora, STMicroelectronics
Vishesh Kumar, Cadence
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CI5 : Automated Test Case Creation for Design Rule Deck Validation (DRDV)
Sharifsab Nadaf, Sankalp Semiconductor
Adarsh Kamkar, Sankalp Semiconductor
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CI6 : Enhanced Layout Performance Using Virtuoso Suite for Electrically Aware Design (EAD)
Shashank Chaturvedi, STMicroelectronics
Shivam Kalla, STMicroelectronics
Vikas Rana, STMicroelectronics
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CI7 : Methodology to Improve Analog Sub-System Layout Utilization
Anantha Kamath,Texas Instruments
Pavankumar Kulkarni, Texas Instruments
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CI8 : Optimizing Analog Design for Layout Dependent Effects on 22FDX
Rajeev Singh, STMicroelectronics
Atul Bhargava, STMicroelectronics
Vishesh Kumar, Cadence
Michel Cote, Cadence
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CI9 : Automatic Cut Metal Shapes Insertion in Advanced-Node Custom Design Process
Ankur Chaplot, Cadence
Sachin S, Cadence
Joyjeet Bose , Cadence
Pardeep Juneja, Cadence
Yashu Gupta, Cadence
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