经验证的质量、低风险、广泛的生态系统和卓越的技术支持使CAST的8051成为许多系统功能的经济高效的解决方案
半导体知识产权提供商CAST今天宣布,杭州晶华微电子股份有限公司——一家领先的模拟混合信号集成电路设计和无晶圆厂半导体供应商——已从CAST获得8051微控制器IP核,用于目前正在开发的一套新芯片。
...The S8051XC3 IP core implements a high-performance, low-energy, 8-bit microcontroller that executes the MCS®51 instruction set and includes a configurable range of features and integrated peripherals.
The core’s sophisticated architecture yields the fastest 8051-compatible 8-bit MCU available anywhere (at the time of its release). It runs with a single clock per machine cycle, and requires an average of 1.5 to 1.8 machine cycles per instruction, depending on configuration. Dhrystone 2.1 tests show it to run from 9.41 to 26.85 times faster than the original 8051 at the same frequency, without requiring an external arithmetic acceleration unit (such as an MDU). Representative 40nm ASIC results have reached 635 MHz for the most advanced version, for an effective speed up of 1,400 times over 80C51 chips. Interrupt latency is a remarkably low two cycles.
The S8051XC3 is also one of the most energy efficient 8-bit processors available. Its small silicon footprint—the CPU size can be 6,000 gates—means very little power leakage. Furthermore, dynamic power of the CPU at a 40nm technology is as low as 2.7μW/MHz, and its higher performance allows clocking at lower frequencies. The core allows energy consumption to be adjusted to the processing workload via dynamic frequency scaling and independent control of the CPU and peripherals clock.
The core’s rich set of optional features and integrated peripherals allows designers to adjust performance and silicon requirements to best match an application’s specific requirements. (Several pre-configured versions at different price points are also available.) Software development is facilitated by a single-wire or JTAG debugging interface, which operates seamlessly within IDEs such as those from IAR and Keil.
This core builds on CAST’s experience with hundreds of 8051 IP customers going back to 1997. Designed for easy reuse in ASICs or FPGAs, the core is strictly synchronous, with positive-edge clocking (except in the optional debug & SPI modules), synchronous or asynchronous reset, and no internal tri-states.
S8051XC3 users can select among a rich set of pre-integrated and pre-verified peripherals and core options. (Verilog defines, e.g. ‘define USE_PMU, are used for this purpose.) Options not included by default but that can be added on request are noted by italics.
Three versions of the core are available, offering a range of capabilities and prices:
The Dhrystone 2.1 benchmark score varies from 0.088 to 0.252 DMIPS/MHz, which translates to speed improvements from 9.4 to 26.85 times over the standard 80C51 assuming the same clock frequency, or 500x to more than 1,400 times increase when the S8051XC3 is clocked at 635MHz.
Sample Dhrystone 2.1 benchmark results are as follows.
Version |
DMIPS/MHz |
80C51 Ratio |
S8051XC3-F |
0.252 |
26.8 |
S8051XC3-C |
0.147 |
15.6 |
S8051XC3-A |
0.088 |
9.4 |
Reference designs have been evaluated in a variety of technologies. The following are sample results for the cores CPU using a 40nm ASIC technology.
Version |
Maximum Speed |
Minimum Area |
S8051XC3-F |
630 MHz |
12.5k gates |
S8051XC3-C |
660 MHz |
10k gates |
S8051XC3-A |
880 MHz |
6.2k gates |
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available; contact CAST Sales.
The core is available in Verilog RTL or as targeted FPGA netlist, and its deliverables include everything required for a successful implementation, including a behavioral model, an automated constrained random verification (CRV) test-bench, comprehensive documentation, and sample synthesis and simulation scripts. Hardware debug pods and reference design boards are also available.
Engineered by Silesia Devices.
IAR Systems Embedded Workbench for 8051
Lauterbach Debug and Trace Solutions
Easily evaluate this 8051's features and performance in your own environment with the
Talos Series Evaluation Kit for 8051s.
Understanding Interrupt Latency in Modern 8051s
by Nikos Zervas at ChipEstimate.com