D&R News Alert
May 22nd, 2025


Welcome to the issue of May 22nd, 2025 of D&R SoC News Alert, our email update to provide you with the latest news and information in the System-On-Chip Community.

Dolphin Design
 PowerStudio, the PMU Builder
• Shrink development time: automatic generation of RTL & UPF
• Enhance reliability: correct-by-construction design approach
• Improve power efficiency: power network & controller optimizer

Learn More >>

Foundry News
■ GlobalFoundries partners with A*STAR to accelerate advanced packaging innovation
3D Packaging
■ Advanced IC Packaging: The Roadmap to 3D IC Semiconductor Scaling
DisplayPort & eDP 1.4, MIPI DSI-2 & D-PHY, ASIL Qualified IP Cores
• Leaders in Interface Semiconductor IP
• Silicon-Proven to 5nm TSMC, UMC, GF, SMIC
• Customizable PHY & Controller IP
• Hot IP: 1G Ethernet BaseT1, HDMI, USB

Design and Monitoring
■ Siemens to bring advanced timing constraint capabilities to EDA design flow with Excellicon acquisition
■ Movellus Claims First On-Die Power Delivery Network Analyzer
RISC-V
■ Boosting RISC-V SoC performance for AI and ML applications
■ SiFive Collaborates with Red Hat to Support Red Hat Enterprise Linux for RISC-V
■ The RISC-V World Sees Changes, Milestones, and Innovations
Secure-IC
Securyzr™ iSSP: Robust Lifecycle Security for Modern SoCs
  • End to End protection for devices from design to decommission
  • Securyzr™ iSSP enables first provisioning, assets secure updates, threats monitoring, etc
  • Manage vulnerabilities via PSIRT
  • Compliant with major regulations: EU CRA, NIST, UNECE, PSTI...
>> READ MORE >> WATCH THE VIDEO

Artificial Intelligence
■ NVIDIA Unveils NVLink Fusion for Industry to Build Semi-Custom AI Infrastructure With NVIDIA Partner Ecosystem
■ sureCore extends its sureFIT design service to include custom memory solutions for AI applications
■ Expedera’s Origin Evolution NPU IP Brings Generative AI to Edge Devices
■ BrainChip CTO to Present on Architectural Innovation for Low-Power AI at the Embedded Vision Summit
■ Infineon to revolutionize power delivery architecture for future AI server racks with NVIDIA
■ Programmable AI Silicon Would Help Meet AI Workload Demand
■ Enhancing Edge AI with the Newest Class of Processor: Tensilica NeuroEdge 130 AICP - by Cadence
Satellite
■ EnSilica expands satcoms user terminal portfolio with dual-beam, dual-polarization Ku-band analogue beamformer chipset
■ Steering the future: advanced satellite communications phased arrays with GF 45RFSOI, 45RFE and 130NSX
5G
■ What is the Right Metric to Understand 5G Processing Throughput? Well, it’s not Peak Speed... - By AccelerComm
eFPGA
■ Cost-Optimized PolarFire® Core FPGAs and SoCs from Microchip Technology Deliver High Performance with a 30% Lower Price Tag
Photonics
■ Imec and TNO Launch Holst Centre Photonics Lab to Accelerate Integrated Photonics Innovation in the Netherlands
Green Electronics
■ Sustainable supply chain: training for Leonardo’s suppliers
What’s new in Green Electronics?
Partner News
■ Six HCLTech campuses in India receive the coveted TRUE Zero Waste Platinum Certification
Business News
■ Intel eyes sale of network and edge unit as cost-cutting continues: report
Visit the freshly renewed B2B unique worldwide portal

>> www.design-reuse.com

listing the best qualified resources for designing IP based Electronic systems








ARC NPX6 NPU IP Processor: AI Data Compression Option (OCP-MX)
• Enhanced data efficiency
• Improved computational performance

New IP
• Cryptographic Cores IP by Crypto Quantique
• ARC NPX6 NPU IP Processor: AI Data Compression Option (OCP-MX) by Synopsys
• Origin Evolution for Edge by Expedera
• UCIe Chiplet PHY & Controller by Innosilicon

What they said at
IP SoC Silicon Valley 25

Efficient by Design: Revolutionizing Power Management in SoCs
Floriberto Lima, CEO, SiliconGate

Cost-effective AI MCU featuring a standard logic compatible embedded flash memory
Peter Song, CEO and Co-Founder, ANAFLASH Inc.

How do you select the right memory architecture and choose between LPDDR, GDDR, and HBM?
Dirk Seidel, Marketing Director, Innosilicon

Building Tomorrow Today: Innovating with IP
Ook Kim, CEO, 4lynx, Inc.

makeChip: an accessible, cost-effective, and cloud-based Chip Design Platform
Florian Bilstein, Director Design Service, Racyics GmbH

Challenges of Porting ASIC IP Cores to FPGA: Tricky but Worthwhile!
Ettore Giliberti, Senior Staff Application Engineer, SmartDV Technologies

DFT Ready in RTL Level with SOC Canvas
Ahchan Kim, CTO, ITDA Semiconductor Co., Ltd.

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