D&R News Alert
Innovation in the Semiconductor World
June 29th, 2026

Welcome to the issue of June 29th, 2026 of D&R SoC News Alert, our email update to provide you with the latest news and information in the System-On-Chip Community.

Mixel has the most comprehensive portfolio
of production-ready MIPI PHY IP
• Widest adoption of MIPI D-PHY, C-PHY, and M-PHY in the industry
• Silicon-proven in 12 different nodes and in 9 different foundries
• Now supporting Automotive SerDes Alliance Motion Link (ASA-ML) IP
Join Mixel at the Design Automation Conference (DAC) 2026
Booth #1155 – July 27-29

Foundry Ecosystem News
■ Advanced USB Connectivity IP Validated on N2P Process Technology
■ TSMC Is Raising 7nm Chip Prices Up To 10% As Expansion Builds
■ Global Foundry 2.0 Revenue Rises 23% YoY in Q1 2026 as AI Continues to Boost Demand
Technology News
■ IBM Unveils Sub-1nm Chip Tech with 50% Performance Boost
SmartDV
SmartDV OpenGMSL
Design IP and Verification IP
• Design IP and VIP for the OpenGMSL v3.0 specification
• GMSL2/3 interoperability for automotive video & sensor links
• Early traction with Japan semiconductor firms
• Early access for teams ahead of compliance rollout
Discover more at smartdvtech.com >>

Chiplets
■ Beyond Moore’s Law: Heterogeneous Computing and AI SoCs
■ When does it make sense to move from a monolithic ASIC to a chiplet-based design?
Design Platforms
■ Murata and Synopsys collaborate to streamline simulation workflows for electronics designers
■ DDR Verification Challenges in Modern Chip Design
Arasan
Arasan Total UFS 5.0 IP
  • Supports high speed data transfer data rates up to 46.6 Gb/s
  • High Performance, Built for AI, Automotive & Flagship Devices
  • ASIC & FPGA Ready
Learn More

Memory and Storage
■ Advancing Flash Memory Performance for the Edge AI Era
■ M31 talks about 12 FFC Multi-Port Register Array
RISC-V
■ Sovereign European chips could become a RISC-V-based reality
Artificial Intelligence
■ EdgeAI Licensed Andes Technology CPU IP to Power Next-Generation Edge AI Neuromorphic Solution
■ Jim Keller: ‘AI Still Obeys the Old Laws of Compute’
■ PREVAIL: A Unique European Testing Platform for Edge AI
■ NVIDIA Vera Rubin Delivers World-Class Supercomputers for Science
Security
■ What the Cyber Resilience Act means for the future of chip design
■ The quantum countdown: what the new White House EO 14409 means for PQC
Automotive
■ Floadia Releases High-Performance Automotive Embedded Flash IP on Leading Foundry’s 90BCD Platform
Internet of Things
■ Cellular IoT Market Growth to Reach 5.9 Billion Connections by 2035, Says Omdia
Multimedia IP
■ TEVIOS Becomes Official Distributor of intoPIX AV Solutions
Partner News
■ Ceva CEO Amir Panush Named “Artificial Intelligence Company CEO of the Year” in 2026 AI Breakthrough Awards Program
■ M31 Joins “2026 TALENT, in Taiwan – Talent Sustainability Action Alliance”
■ EnSilica set to post record results after “very successful year”
■ Renesas Promotes Gaurang Shah to Senior Vice President
■ SkyeChip profit forecast to grow at 48% CAGR from FY26 to FY29
Business News
■ Synaptics Acquisition by Onsemi Affirms Edge AI Is for Real
■ South Korea nears announcement on new semiconductor production cluster outside Greater Seoul
■ India as the Emerging Global Semiconductor GCC Hub




Chips'n media
AV2 Decoder IP
Available Now!

• AV2/AV1/VP9/VVC/HEVC/AVC up to 8K
• 8K 60fps@1GHz
• Bus latency tolerance up to 1200 cycles
• I/P/B frame, FBC, Multi-instance
 >> More about WAVE63F1


Synopsys UFS 4.0 G5 Host Controller with IE and Unipro
• Enables maximized DMA throughput
• Pre-configured for up to 32 task requests in Legacy Single Door Bell mode

What they said at
IP SoC Silicon Valley 26

Securing Physical AI Systems: From Device Identity to Distributed Trust
Ranga Desikachari, Director of Engineering, Crypto Quantique

From Monolithic SoCs to Chiplets: A new Hardware Security Paradigm
Berardino Carnevale, Senior Technical Marketing and Product Manager, Rambus, Inc.

Hardware-Software Co-Design and Side-Channel Resilience Challenges in Post-Quantum Cryptography IP
Reza Azarderakhsh;Patrick Manning, CEO, PQSecure Technologies

Future-Proofing SoCs: eFPGA IP Use Cases and Integration Made Predictable
Trey Peterson, Field Application Engineer, QuickLogic Corp.

Why Aren't You Considering eFPGA for Your Next ASIC? (And What It's Costing You)
Jayson Bethurem, VP, Business Development, Menta

Why Now Is A Critical Moment To Think About On-Chip Smarts For Power and Thermal Efficiency
Mahesh Tirupattur, CEO, Analog Bits Inc.

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