Jazz Semiconductor and Legend Design Technology, Inc. Collaborate to Deliver Memory Re-Characterization Capability for Low-Power System-on-Chip Designs

SANTA CLARA, Calif. and NEWPORT BEACH, Calif.--Oct. 5, 2005--Legend Design Technology, Inc., a leading provider of IP characterization and circuit simulation software, today announced that Jazz Semiconductor, an independent wafer foundry focused primarily on specialty CMOS process technologies, has adopted its CharFlo-Memory!(TM) and MSIM(R) tools for re-characterizing on-chip memory instance models at various process, voltage and temperature (PVT) corners.

"For low-power designs, our customers need to lower power consumption, which can be achieved by minimizing the voltage supply, which is different from the voltage in corner models provided by memory compiler vendors," said Rajiv Gupta, director of IP and design services at Jazz Semiconductor. "Therefore, timing and power models of memory instances must be re-characterized to prevent design failures and low yields. Legend's CharFlo-Memory! has automated the process of accurately and efficiently re-characterizing memory instances at any voltage supply. Jazz also uses CharFlo-Memory! to quantify the mismatch due to PVT change, and then determines whether to re-characterize those on-chip memory instances."

On-chip noise is a limiting factor for lowering the voltage supply in low-power designs. CharFlo-Memory! has provided the capability of optimizing the voltage supply by analyzing the 'signal versus noise margin' at all possible voltage levels. The optimized voltage supply will ensure that the signals (e.g. sense-amplifier input) are stronger than the noise margin, while keeping the power consumption as low as possible.

For large memory instances, layout parasitic extraction can take an excessive amount of time and generate huge amounts of circuit data. By providing 'critical nets' to extract, CharFlo-Memory! enables layout parasitic extraction on critical-path circuits only. Since the 'critical nets' are less than 1% of the total nets on chip, the time-consuming layout parasitic extraction can be done in a much shorter time, with a significant decrease in the amount of extracted circuit data.

"The quality and reliability of embedded memory is essential for the success of SOC designs," said You-Pang Wei, president and chief executive officer of Legend Design Technology. "Legend is pleased to have our CharFlo-Memory! and MSIM tools chosen by Jazz Semiconductor, a leader in advanced analog SOC designs, to enable Jazz customers to re-characterize on-chip memory instance models at any new PVT (process, voltage and temperature) corners, for efficient low-power design."

About Jazz Semiconductor

Jazz Semiconductor is an independent wafer foundry focused primarily on specialty CMOS process technologies, including SiGe BiCMOS and RFCMOS for the manufacture of highly integrated analog and mixed-signal semiconductor devices. Jazz's executive offices and its U.S. wafer fabrication facilities are located in Newport Beach, California. Jazz has expanded its wafer capacity in China through manufacturing partnerships with Advanced Semiconductor Manufacturing Corporation and Hua Hong NEC Electronics Co., Ltd. Contact Jazz Semiconductor at www.jazzsemi.com.

About Legend Design Technology, Inc.

Legend Design Technology Inc. is a leading provider of circuit simulation and semiconductor IP characterization software for SoC designs. With an emphasis on productivity and value, Legend's CharFlo-Memory! toolset revolutionizes the time-consuming and error-prone processes associated with characterization. MSIM is Legend's high-accuracy SPICE circuit simulator with great convergence and extensive model support. Turbo-MSIM is Legend's high-speed and high-capacity circuit simulator ideal for timing and power simulation, and function verification. Both simulators are well designed for nanometer technology challenges, and provide excellent price performance. For more information, visit www.LegendDesign.com.