| SANTA CLARA, Calif. — Constituting as much as 90 percent of the effort expended on new designs, software content and verification strategy must be considered at the earliest stages, according Mark Gogolewski, chief technology officer at Denali Software Inc. Delivering a keynote address at Denali's Memcon event here Wednesday (Oct. 12), Gogolewski said design costs are skyrocketing, mostly due to increased time and effort spent on architecture and verification. Another challenge is securing intellectual property and making it interoperable, something that is straining the relationship between the EDA community and the semiconductor industry. "Putting more engineers on the project does not necessarily solve the problem," said Gogolewski, who noted that IP blocks are still painstakingly stitched together, largely through "brute force." Citing data compiled by Philips Semiconductors, Gogolewski said the software content of system-on-chips (SoCs) is growing 10-fold every six years. Design starts are trending downward, he said, because design costs are rising. He said a new chip design requires a $100 million market opportunity, something he noted is rare. According to some metrics, Gogolewski said, software development costs have surpassed hardware development costs. "We often hear that verification is 70 percent of the total design effort, but not about the other 100 percent going into software," Gogolewski said. Part of the problem, Gogolewski said, is that the industry is expending so much energy fitting together IP blocks and then verifying interoperability. For example, he said, there is no guarantee that one PCI bus core can be swapped out for another. "As an industry, we cannot let this continue," he said. Gogolewski called for closer industry collaboration around bus and interface standards. He pointed to PCI Express as a shining example, noting that Intel Corp.'s early embrace of the spec pushed much of the industry to support and develop it. Too often, Gogolewski said, standards efforts result in a "piece of paper" describing the agreed upon components of a standard. That's far from a complete, workable standard, he added. Gogolewski gave the industry high marks for providing IP for microprocessors, digital signal processors (DSPs) and embedded memories. But he gave the industry a grade of "incomplete" for providing IP for standard interfaces and on-chip buses. Gogolewski said the industry has not come close to achieving the "dream of SoC," which he defined as the ability to stitch together plug-and-play IP with perfect connectivity. "Today," Gogolewski said, "we can't always find the pieces that we need, and it's hard to make them fit together." | 
