Embedded CPUs break out baseband functions for 3G apps

Embedded CPUs break out baseband functions for 3G apps
By Anthony Cataldo, EE Times
September 22, 2000 (11:41 a.m. EST)
URL: http://www.eetimes.com/story/OEG20000922S0017

TOKYO — Semiconductor makers are racing to develop a class of general-purpose embedded processors geared for third-generation wireless systems and separate from traditional baseband components. The "application processors" aim to stake out new turf in wireless silicon, powering smart cellular phones and an emerging class of Internet appliances.

Intel Corp., NEC Electron Devices, Mitsubishi Electric Corp. and the duo of Hitachi Ltd. and STMicroelectronics are all developing high-performance, low-power processors that could play a role in that emerging market. But a top technologist from Texas Instruments Inc. said the architectures are playing catch-up with the hybrid DSP/RISC architecture that TI defined last year.

Intel, the most vocal evangelist for the application processor, rolled out its StrongARM-based XScale processor in Japan this past week as the archetype of the standalone application processor.

In Japan, where 3G services ar e set to launch next spring, the idea appears to be catching on. At least two Japanese cellular phone makers — Mitsubishi Electric Corp. and NEC Corp. — have announced their intentions to use Intel's current StrongARM in 3G phones. Now both companies' chip divisions are developing their own application processors for next-generation handsets.

Japan's chip makers sense a silicon opportunity brewing in the second-generation cellular data services popularized by NTT Docomo's widely used i-Mode service here. Docomo expects to roll out 3G services using wideband CDMA technology next spring.

"In Japan, we have an advantage because of i-Mode," said Keiichi Shimakura, deputy vice president of NEC Electron Devices. "We have the know-how, and we can see new applications coming, like movies and sound. Our mobile division is a major supplier in Japan, and we can develop that chip."

Shimakura wouldn't say when the processor might be introduced, but the functional components he described herald a cla ss of wireless Internet appliances that will be heavy in multimedia content and connectivity. The processor will have either an ARM or the company's proprietary V850 bit processor at the core, depending on the customer's request, and will include peripherals supporting IEEE 1394, USB, MPEG-4 acceleration and Bluetooth, Shimakura said.

That breaks with NEC's conventional approach to cell phone design, in which the CPU is tightly coupled with the digital signal processor in the baseband. The conventional baseband design will continue, but there will be a separate design for an application processor and middleware.

"The baseband will be done in one chip, but with W-CDMA the applications will increase rapidly. For that reason we will have to come up with a baseband plus an application chip," Shimakura said.

NEC's research division, meanwhile, is pushing forward with a CPU design that could be a candidate for use as a general-purpose processor in wireless devices. Based on NEC's V830 core, the MP98 i s a two-issue superscalar architecture with four processing elements that can operate in parallel. At the device level, it uses low-voltage threshold transistors and power management circuitry to control leakage current. Using 0.15-micron process rules, the prototype is still too large, but it could become practical at 0.12-micron design rules, said Masao Fukuma, general manager of NEC's Silicon System Research Laboratories.

Billion instructions/second

"At 0.12 micron, we can get 1 giga-instructions per second at 300 milliwatts," he said. "I believe it will be a real product. By 2003, the market will explode."

Mitsubishi, meanwhile, is devising its own processor for cellular phones. Like Intel's and NEC's architectures, Mitsubishi's processor will be functionally separate from the baseband. The device will be able to process 1 billion instructions per second and will be geared to take on such applications as Java, said Koichi Nagasawa, group president of the semiconductor unit of Mitsu bishi Electric Corp.

Nagasawa, however, was quick to point out that the move to application processors could take several years. He expects the current baseband architecture to go through at least another iteration before a radical change in the design of W-CDMA terminals is needed. "For W-CDMA, it will be done in steps. First, next year, we will use an improved version of the architecture using our M32R processor and D10V DSP. Maybe by 2002 we're going to have to change the total concept."

Other contenders wait in the wings. By the first half of next year, Hitachi and STMicro expect to roll out their SH-5 processor, a single-instruction, multiple-data (SIMD) architecture that can process 64-, 32-, and 16-bit-wide instructions. Set to be manufactured on a 0.15-micron process, the device will offer a high Mips/W ratio that will suit it for such applications as 3G cellular, said Masahiko Ogirima, senior vice president of Hitachi Semiconductor & Integrated Circuits.

The SH-5 could secure a foothol d for Hitachi's CPUs in cell phones when 3G services roll out. While the company has a presence in power amplifiers and high-frequency signal processing at the front end, it has been eclipsed by ARM processors in baseband designs, Ogirima said.

Debate revisited

The application processor concept revives the DSP-vs.-general-purpose-processor debate, pitting Intel, with the X86 and now the XScale, against DSP giant Texas Instruments. But both companies are actually edging toward a middle ground that embraces both DSP and RISC.

Intel has teamed with Analog Devices Inc. on a DSP, set to ship later this year, that will pair with the XScale in wireless handsets. And TI 18 months ago introduced the Open Multimedia Applications Platform (OMAP), which combines an ARM microprocessor core with a TI DSP.

ARM-based cores are used today in cellular basebands to handle control functions and communications protocols. But when 3G phones arrive, those processors will be too busy with Layer 2 and Lay er 3 communications functions and will have little headroom left for such applications as streaming video, applets and browsers, said Patrick Reilly, director of Intel's Wireless Computing Enhancement Architecture Lab. "You can't fully load this CPU with a bunch of apps. You can put a few, but not much."

The digital signal processor, for its part, can be pushed to handle higher voice bandwidth or streaming audio, like MP3, but most applications need more than a "brain-dead" processor designed for repetitive tasks, Reilly said.

Ron Smith, general manager of Intel's wireless communications and computing group, said he expects the first wireless systems using XScale processors to appear by the second half of 2001.

"The applications and client should be developed separately from the communications stack," Smith said. "We want to free them so that they can develop at their own pace."

As part of the plan, Intel will fashion a set of common inter faces and APIs and work with software developers to build a base of applications that can take advantage of the faster wireless services and more general-purpose CPU.

DSPs require code to be written in assembly language and are geared for processing bit streams, Intel's Smith said. A better option is to use a general-purpose CPU and a common set of APIs. "We want apps written in bytes, not in bit streams," Smith said.

To that end, Intel envisions high-end 3G platforms using a second XScale application processor that would be linked to various peripherals, memory, co-processing functions and Bluetooth short-range wireless functions. The processor would be functionally independent of the baseband, so that applications would not be held back by programming issues related to the communications stack.

The distinction between the roles of the DSP and the general-purpose processor should come to light by the end of the year, when Intel introduces its first XScale-based processors and the DSP archit ecture it is co-developing with Analog Devices.

At TI, executives said that both RISC and DSP cores will be required for future wireless systems but that they can be combined on one die or module, a scheme the company's OMAP architecture aims to address. OMAP packs an embedded TMS320C55X DSP with a 130-MHz ARM RISC processor and high-speed dedicated logic blocks on a chip in a 0.15-micron-effective CMOS process technology. To date the architecture has garnered support from Ericsson, Sony and Nokia on the hardware side and from Microsoft (for Windows CE) and Symbian (for Epoc) on the software side.

"OMAP is an architecture that we believe is ideally suited to applications development," said Mike McMahan, director of R&D for TI's wireless group. "The architecture combines a RISC and a DSP, using both where appropriate. It's essential to have an architecture that's DSP-based to handle the kinds of applications that will be encountered.

"Most applications do require both sets of expertise, so from t he standpoint of efficiency, particularly power efficiency, it's the best approach, and the endorsements we've received validate that," McMahan said. "Our customers have had a lot of experience in this marketplace and understand the requirements; if I were Intel, I'd listen to what they're [saying]."

As to ease of software development, McMahan pointed to the raft of third-party applications that have already been turned out. "I'm not sure why development speed and assembly and efficiency should be an issue, as the applications Intel mentions already exist for our DSPs. And they can be programmed in high-level languages," he said.

The general-purpose processors will also face some competition from a new class of VLIW-based DSPs. Fujitsu, for one, last year announced its FR-V architecture, which provides instruction-level parallelism and supports 16-bit instructions, 32-bit integers, DSP and floating-point instructions. The FR300, a low-power version of the FR-V intended for W-CDMA phones, will perform voice compression and decompression plus codec functions for MPEG-4 video. And unlike most DSPs, the device can be programmed using C/C++ tools, according to Fujitsu.

— Additional reporting by Patrick Mannion.