Simply RISC ships the S1 Core, a 64-bit Wishbone-compliant CPU Core based upon the OpenSPARC T1 microprocessor released by Sun Microsystems

Sep 14, 2006 -- Simply RISC has shipped the S1 Core, a 64-bit Wishbone-compliant CPU Core based upon the OpenSPARC T1 microprocessor released by Sun Microsystems few months ago.

The S1 Core is released under the same license of the T1, the GNU General Public License (GPL); the design is freely downloadable from the Simply RISC website at www.srisc.com and no registration is required.

One of the main purposes of Simply RISC was to keep the S1 Core environment as simple as possible to encourage developers: most of the simulation and synthesis activities are now performed with simple push-button scripts and system requirements are very easy to meet.

The environment can run on any Unix/Linux box and no commercial tools are required, since both simulation and synthesis of the Verilog files of the design can be performed using the free software Icarus Verilog.

Due to its Wishbone-compliant bus interface the S1 Core can be easily interconnected to several cores freely available on OpenCores.org to build up a System-on-a-Chip.

Due to the collaborative nature of the GPL license Simply RISC plans to add new features to the S1 Core and test them extensively over the next months with the help of the community.