Evatronix to host technical seminars at the company stand during Electronica 2006

Update: Cadence Completes Acquisition of Evatronix IP Business (Jun 13, 2013)

Industry experts share their ideas about system-on-chip engineering with Electronica visitors

Bielsko-Bia³a & Gliwice, Poland, 6th November 2006, Evatronix S.A., the silicon Intellectual Property (IP) provider announced today that free seminars
about system-on-chip design, related standards and low cost IC prototyping technologies will be hosted daily from November 14th through 17th , during Electronica 2006 trade show in Munich, at Evatronix stand (Hall: A5, Stand: 331).

Speakers and presentations:
Mr. Oliver Bringmann, representing the European SystemC Users Group, will deliver two presentations. The first one will introduce into the basic concepts of the SystemC language to the audience, with a special emphasis on the transaction-level modeling (TLM), while the other one will show a systematic design process for SoCs and distributed embedded systems starting with a high level SystemC specification.  

Mr. Mark Burton will represent The Open Core Protocol International Partnership, with a speech “The OCP IP-core interface Standard: Supporting ESL”, in which he will talk about the OCP-IP vision, infrastructure and working groups and will use the Texas Instruments OMAP platform as an illustration of OCP-IP standard applications .

Mr. Carl Das from EUROPRACTICE IC Service, in his presentation “Affordable access to ASICs (IP, prototyping and volume)", will challenge the widespread opinion that ASICs cannot be economically justified for small to medium volume projects.

Mr. Adam Morawiec, director of the European Electronic Chips & Systems design Initiative (ECSI), will focus on ECSI activities aimed at organizing research projects under EU 7th Framework Program to address unsolved electronic design problems and will report on research on SoC design methodologies carried out by the SPRINT (6FP project) consortium.

 “We are proud to host at our stand the representatives of organizations that contribute to system-on-chip design related standards as well as those who facilitate access of SMEs to SoC prototyping & low volume production and to research projects funded by the EU. We invite all Electronica 2006 visitors interested in the presented subjects to take part
in the seminars and to share their SoC development experiences with other participants in informal discussions. It will set up the stage for cooperation that may make SoC design more manageable.” - said Wojciech Sakowski, Evatronix president & chief strategy officer.

The seminar program will be complemented with Evatronix technical presentations highlighting the company new products. Attendees of any seminar will get a complete information package with all presentations included on a CD. Additionally, all seminar guests will take part in a daily prize drawing. For a detailed schedule of seminars and more information about Evatronix presence at Electronica 2006, please visit www.evatronix.pl. Registration will take place on-site, but in case you want to pre-register for a particular seminar, please contact Evatronix.

About Evatronix

Evatronix SA, headquartered in Bielsko-Biala, Poland, develops electronic virtual components (IP cores) and provides electronic design services in the field of SoC engineering. The company’s main design office is located in Gliwice (Poland) that guarantees easy access to a talent pool of graduates from the Silesian University of Technology. Evatronix IP cores are available worldwide through the sales channels of its strategic distribution partner CAST, Inc. (New Jersey, USA). In Switzerland and the European Union countries (excluding UK) Evatronix also operates a direct sales channel. Design services are marketed by the company directly, too. More information on Evatronix and its product portfolio can be found at the company web site: www.evatronix.pl.