Renesas Technology Develops Promising Technology for Implementing On-Chip SOI SRAM of 32-Nanometer Generation and Beyond

Technology for improving operation margins by means of individual control of transistor substrate (body) potential

Tokyo, June 12, 2007 −− Renesas Technology Corp. today announced the development of a technology that is effective in implementing SRAM in processes of the 32 nm (nanometer) generation and beyond, for on-chip SRAM incorporated in a microprocessor or SoC (system-on-a-chip).

The newly developed technology uses SOI (Silicon On Insulator) technology*1, and individually controls the potential of the bodies − that is, substrate parts − of the three kinds of transistors composing SRAM, enabling SRAM operation margins to be greatly extended.

Experimental fabrication and evaluation of 2-Mbit SRAMs using a 65 nm CMOS process employing this technology confirmed an approximate 100 mV improvement in the operating lower-limit voltage compared with non-use of this technology. Furthermore, the read margin (Static Noise Margin: SNM*2) − an important SRAM operation margin indicator − was improved by approximately 16%, and the write margin by approximately 20%, while transistor electrical characteristic variations were resulted in approximately 19% reduction.

SNM falls as processes become finer. However, in 32 nm and 22 nm generation simulations, improvements in SNM of approximately 27% for 32 nm and approximately 49% for 22 nm were confirmed as compared with non-use of this technology, representing achievement of a level equivalent to that of a 65 nm process. This technology can thus be said to hold promise for the realization of SRAM of the 32 nm generation and beyond.

Renesas Technology will present these results at the 2007 Symposium on VLSI Technology being held in Kyoto from June 12, 2007.

Background

With the approach of the ubiquitous computing society, the ever increasing functionality and performance of various kinds of products are being accompanied by demands for lower power consumption. In order to create such products, the microprocessors and SoCs at their heart have become faster and more highly integrated through the use of finer processes. However, fabrication variations have become relatively large as processes become finer, resulting in increased variations in the electrical characteristics of transistors. In turn, variations in threshold voltage − the borderline voltage at which a transistor is turned on or off − reduce operation margins, adversely affecting circuit operation. Consequently, as processes become finer, the industry has undertaken research and development efforts to counter such variations. However, with the 32 nm generation and beyond, the effects on circuit operation of reduced operation margins due to variations are expected to become a far more serious problem, and further technological developments are a major concern.

Details of the Technology

Against this background, Renesas Technology has been pursuing technological development targeting the 32 nm process and beyond, for the 6-transistor type of SRAM circuit that is essential to microprocessors and SoCs, and is also most susceptible to the effects of variations. The technologies adopted and developed in the present case are as follows.

(1)	Use of SOI
	Fabrication variations require atomic-level control, and are extremely difficult to reduce. Therefore, a method of suppressing electrical characteristic variations while assuming the occurrence of fabrication variations is essential, and one effective method of this kind is to control the threshold voltage by applying a voltage to the substrate. However, with bulk silicon*3, multiple transistors are normally formed in areas called wells created on a silicon substrate. With this structure, the substrate potential is applied to multiple transistors, and it is therefore extremely difficult to control individual transistors more precisely. With SOI technology, on the other hand, a transistor is formed in silicon on an insulator film, and therefore transistors can be electrically isolated, and it is easy to implement a structure that allows transistors to be controlled individually. In addition, a so-called partially depleted SOI MOSFET (Metal Oxide Silicon Field Effect Transistor) is used in the present case to apply the body potential.
(2)	Use of hybrid trench isolation structure*4
	A hybrid trench isolation structure is an element isolation structure for a thin film SOI device using proprietary Renesas technology. This hybrid trench isolation structure features both full trench isolation that completely eliminates the SOI layer, and partial trench isolation that enables the body voltage to be controlled by allowing a thin SOI layer to remain under an isolating oxide film, making it possible to apply a different body potential to each transistor.
(3)	Individual and dynamic control technology of body potential
	Operation margins have been increased by controlling the body potential of SRAM component transistors individually and dynamically in line with SRAM operations such as writes and reads.A 6-transistor type SRAM cell is composed of two sets of transistors, each set comprising three kinds of transistor (access, driver, and load). In the present case, in order to facilitate SRAM writes and reads, a technology has been developed that controls the body potential of each transistor by means of the following kinds of connections, improving operation margins. (a) NMOS access transistor and driver transistor control via word line   A word line has a positive potential in an SRAM read or write operation. By connecting a body to a word line, the positive potential of the word line is applied to the body in a write operation. As a result, the threshold voltage of access transistor (NMOS) falls and a large current can flow, enabling the write margin to be improved. (b) PMOS load transistor control via power line   A load transistor (PMOS) is connected to a power line, and the power line potential is made slightly lower in a read than in a write. By this means, the load transistor threshold voltage is lowered in a read, preventing data loss by facilitating current flow. Furthermore, since a positive potential is applied to the body of a driver transistor as described in (a), the threshold voltage falls, and the read input voltage is lowered. These controls enable the read margin to be improved.