eInfochips announces AVM 3.0 & OVM Compliant SystemVerilog AMBA AHB Verification IP

Integration of AMBA AHB AVM 3.0  Ensures Availability of OVM Compliant High-Quality Verification IP for Advanced SystemVerilog Verification

Sunnyvale, CA., and Ahmedabad, India ­ -- June 13, 2008 -- eInfochips, Inc., a leading IP leveraged design services company today announced the availability of the industry's first OVM & AVM 3.0-compliant  AMBA AHB SystemVerilog Verification component. This integration which is a result of a collaborative effort between Mentor Graphics and eInfochips will enable designers to more effectively use key SystemVerilog functionality, and drastically reduce verification cycle times for designs that incorporate standard interfaces such as AMBA. AMBA AHB verification IP provides necessary building blocks for efficient design-under-test (DUT) for module and system-level verification, including comprehensive assertion testing.

"OVM or AVM 3.0-compliance will be the hallmark of all verification IP components in the future," said Nirav Shah, Director of Marketing at eInfochips. "The integration of our existing SV AMBA AHB VIP with AVM libraries will provide our customers the most powerful verification environment to achieve increased productivity and quality and will enable them to leverage all the benefits that OVM and SystemVerilog has to offer for functional verification."

"We are pleased that eInfochips has moved rapidly to offer support for the OVM standard and qualified the support of their verification IP on our Questa verification platform," said Dennis Brophy, Director of Strategic Business Development, Mentor Graphics.  "As a trusted partner, eInfocihps continues to demonstrate leadership in support and development of OVM compliant VIP as the industry rapidly adopts OVM for its superior technology and unmatched openness."

An Open and Interoperable solution to AMBA AHB Verification

eInfochips' AMBA AHB verification component is based on AVM 3.0 ~ OVM that allows coverage driven verification suitable for verifying Master, Slave and AHB  with various combinations. The AHB SV VIP provides all the necessary building blocks to test master/slave DUT with the AHB protocol. The verification component can be easily configured Master, Slave and AHB and allows Module & System-level verification.

Being an OVM-compliant VIP ensures that the SystemVerilog AMBA AHB VIP can run on any IEEE 1800 standard simulators and conforms to true open source license agreement. The VIP has been thoroughly verified on Mentor Graphics' Questa Verification Platform. Designers can also benefit with the VIP interoperability features enabling plug and play functionality across ecosystems, simulators and other higher level languages.

AVM 3.0-compliance integrates advanced verification techniques like constrained-random stimulus, functional coverage and assertions into a single transaction level modeling (TLM)-based framework implemented in both SystemC and SystemVerilog in the AMBA AHB VIP, apart from improved management and reporting features and more top-level environments for integrating 3rd-party IP Cores.

Availability

Deliverables include verification component code with user guide, release notes and test suite. eInfochips' verification experts meet customer requirements related to integrating VC's into test environment and other support related issues. The verification component is available from eInfochips, for pricing details about AHB SystemVerilog VIP contact sales@einfochips.com , Please visit http://einfochips.com/services/OVM_IP.html for more information.

About the AVM

Announced in May 2006, the Mentor Graphics AVM is the first true system-level-to-RTL verification methodology, integrating advanced verification techniques like constrained-random stimulus, functional coverage and assertions into a single transaction level modeling (TLM)-based framework implemented in both SystemC and SystemVerilog. The AVM open-source library features an object-oriented coding style to reduce the amount of testbench code and a modular architecture to enable reuse. The AVM consists of the AVM Cookbook, a "how-to" guide for getting started, and source code for base class libraries, utilities, and implementation examples written in both SystemC and SystemVerilog. To access the Mentor Graphics AVM visit: http://www.mentor.com/go/cookbook

About the OVM

The OVM is the result of joint development between Cadence and Mentor Graphics to facilitate true SystemVerilog interoperability with a standard library and a proven methodology. Completely open, it combines the best of the Cadence® Incisive® Plan-to-Closure Universal Reuse Methodology (URM) and the Mentor Advanced Verification Methodology (AVM), and is usable on two-thirds of the world's SystemVerilog simulators. The OVM will also facilitate the development and usage of plug-and-play verification IP (VIP) written in SystemVerilog (IEEE 1800). For more information please visit: http://www.ovmworld.org/index.php

About eInfochips

eInfochips is a leading provider of ASIC/SoC design & verification services, embedded system solutions,  IP cores and application software services. eInfochips' capabilities extend from Specification to System, with knowledge spanning silicon design & verification, physical design, embedded product design and application software and IP Cores. The company's design centers have delivered SoC and embedded solutions to a variety of customers thus increasing cost-effectiveness, reducing time-to-market and growing their market strength.