Atrenta Announces "SpyGlass(R) Clean" Flow with Leading ESL Synthesis Providers

SpyLinks(TM) Program Initiative Enables High Quality Register Transfer Level (RTL) Output from Electronic System Level (ESL) Synthesis Tools

SAN JOSE, Calif. -- November 10, 2008 -- Atrenta Inc., the leading provider of Early Design Closure® solutions to radically improve design efficiency throughout the IC design flow, today announced the expansion of its “SpyGlass® clean RTL” efforts to the ESL synthesis flow. Atrenta has formed partnerships with leading ESL synthesis tools providers Forte Design Systems, Synfora, Esterel EDA Technologies, and AutoESL Design Technologies under its SpyLinks™ program. The program ensures that the RTL output from the partners is compliant with SpyGlass and meets quality requirements on a wide range of issues such as coding standards, synthesizability, simulation readiness, clock management and power management. The end goal is to create a healthier and more robust environment for system-on-chip (SoC) design starting at ESL.

“The number of customers using ESL synthesis as a bridge between system-level design and chip implementation is rapidly growing,” said Piyush Sancheti, senior director of business development at Atrenta. “Atrenta’s SpyGlass has become the industry standard for establishing clean RTL. Our goal is to enable a similar level of quality for RTL generated from ESL synthesis, resulting in faster and smoother implementation closure. We are working with the industry leaders in this space and will continue to expand the collaboration based on the needs of our common customers.”

“Forte’s Cynthesizer™ and Atrenta’s SpyGlass are integral parts of the SystemC-based ESL deployment flow found in many of the top ten systems and semiconductor companies around the world,” said Brett Cline, vice president of marketing and sales at Forte. “Our silicon proven joint solution increases productivity and overall design quality while minimizing risks for both control and datapath designs.”

“Top-tier customers are using PICO Extreme and Atrenta SpyGlass to design complex IP blocks for consumer SoCs,” said Vinod Kathail, chief technology officer and founder of Synfora. “The combination of these two powerful technologies allows our customers to ensure that the quality of RTL meets their expectations, and to perform power estimation and optimization, which are major concerns for our customers. The joint solution allows our customers to do ‘architecture exploration,’ providing unequaled insight into performance, area and power characteristics early in a design, when analysis and design tradeoffs can have maximum impact. We are very excited about the opportunity to offer our customers the competitive advantages that such a combination affords.”

"Atrenta and Esterel have common customers deploying an ESL flow for wireless handset designs. They use Esterel Studio for control logic and Synfora’s PICO Express for algorithmic synthesis, and perform SpyGlass checks on the automatically generated RTL," said Gunther Siegel, chief technology officer of Esterel EDA Technologies. "Machine generated RTL contains coding styles that may not be acceptable for hand-generated code. Atrenta and Esterel removed the unnecessary debugging for the end-user by working together on our respective tools. We improved Esterel Studio code generation patterns, and Atrenta adapted SpyGlass to better analyze our compiler generated code."

“Our mutual customers are excited about the work we are doing with Atrenta that has resulted in substantially superior quality of RTL, including power optimization via efficient ESL synthesis from our AutoPilot and RTL power estimation from Atrenta’s SpyGlass-Power,” said Professor Jason Cong, chairman of computer science department at UCLA, and founder of AutoESL Design Technologies.

About Atrenta

Atrenta is the leading provider of Early Design Closure® solutions to radically improve design efficiency throughout the IC design flow. Customers benefit from Atrenta tools and methodologies to capture design intent, explore implementation alternatives, validate RTL and optimize designs early, before expensive and time-consuming detailed implementation. With over 140 customers, including the world’s top 10 semiconductor companies, Atrenta provides the most comprehensive solution in the industry for Early Design Closure. For more information, visit www.atrenta.com.