IP News

Synopsys and ARM Team to Deliver Industry's First Mixed-Language Solution for Secure, Portable IP Models

EDINBURGH, SCOTLAND - Nov. 1, 1999 -- IP '99 Conference -- Synopsys, Inc. (NASDAQ: SNPS), and ARM [(LSE:ARM); (Nasdaq:ARMHY)] today announced they will offer the industry's first mixed-language simulation model creation and distribution solution for complex system-on-chip (SoC) designs. The new solution links Synopsys' HDL model compilers into ARM's ModelGen[tm] technology to provide intellectual property (IP) developers with an efficient method of creating and distributing secure sign-off quality design models that integrate IP blocks using both full custom and HDL techniques. This will enable designers to develop validation models of ARM® core-based SoCs, as well as other IP-based solutions, within days of design freeze and long before first silicon.

"The integration of the Synopsys HDL compiler models into the ARM ModelGen environment provides our partners with the industry's most efficient solution for creating complex verification models of ARM core-based designs," said Alistair Greenhill, EDA Business Unit Manager for ARM. "Both ModelGen and Synopsys' Verilog Model Compiler (VMC) have a proven track record of being able to protect high-value IP in a portable format. With the addition of the VHDL Model Compiler (VhMC) into this collaborative solution, our partners will have the industry's first modeling tool that lets them create complex models directly from components designed using mixed design flows, including VHDL, Verilog, and full custom digital."

"ARM continues to demonstrate its commitment to provide its licensees with the all the tools and support that they need to effectively integrate ARM cores with their own proprietary IP," said Geoff Bunza, vice president of the Synopsys Large Systems Technology Group. "As the challenges of integrating complex IP continue to grow, access to flexible modeling solutions such as the one ARM and Synopsys are providing will become a critical element of successful system-on-chip design and verification methodologies."

ARM's ModelGen 4.0 technology, which provides the link to the Synopsys HDL compilers, will be available from ARM for licensing to new users in December. The Synopsys Verilog and VHDL model compilers are available from Synopsys immediately.

Joint Mixed-Language Modeling Solution

The Synopsys HDL compilers generate secure yet portable models of complex IP derived directly from HDL design. The new joint modeling solution enables direct import of Synopsys-compiled HDL blocks, created using either the VMC or the new VhMC, into the ARM ModelGen kernel. The kernel simulates full custom blocks, manages inter-block communication and provides pin-to-pin, back-annotation timing features that can be automatically re-targeted to multiple simulators. ARM's ModelGen tool incorporates a general purpose 'C' based modeling language (MGS) for the modeling of full custom components. MGS can include pure ISO 'C' code, which enables creation of models with enhanced features such as dynamic configuration, or a general software interface as required for bus interface models. ARM supplies fully verified MGS format models to its Partners for all full custom-designed, hard macrocell ARM cores.

About Synopsys, Inc

Synopsys, Inc. (Nasdaq: SNPS) is a leading supplier of electronic design automation (EDA) solutions to the global electronic market. The company provides comprehensive design technologies to creators of advanced integrated circuits, electronic systems and systems-on-a-chip. Synopsys also provides consulting services and support to its customers to streamline the overall design process and accelerate time-to-market. Additional information about Synopsys is available at http://www.synopsys.com.

About ARM

ARM, a leading intellectual property (IP) provider, licenses high-performance, low-cost, power-efficient RISC processors, peripherals, and system-chip designs to leading international electronics companies. ARM also provides comprehensive support required in developing a complete system. ARM s microprocessor cores are rapidly becoming the volume RISC standard in such markets as portable communications, hand-held computing, multimedia digital consumer and embedded solutions. More information is available at http://www.arm.com

Synopsys, Logic Modeling, Cyclone and Synopsys Eaglei are registered trademarks and VMC, VCS, VSS, SWIFT and VERA are trademarks of Synopsys, Inc. ARM, ARM Powered, Thumb and StrongARM are registered trademarks of ARM Limited. ModelGen is a trademark of ARM Limited.
 
 

Editorial Contacts:

Julie Seymour ARM Tel: +1 408 579 2234 julie.seymour@arm.com

Diane Landers Synopsys, Inc. 503/531-2252 dianel@synopsys.com

 
 
 

Previous Page