Palmchip Introduces New GreenLite™ II Family of Complete System-On-Chip IP Solutions for Disk Drive Control

IP News For Information Contact:

Palmchip Corporation Melissa Jones  Vice President, Marketing  (408) 487-9661  mjones@palmchip.com

Cain Communications, Inc. Sylvia Tam (408) 341-8974 sylvia-tam@caincomm.com

Palmchip Introduces New GreenLite™ II Family of Complete System-On-Chip IP Solutions for Disk Drive Control

Four different designs targeted at dramatically reducing development time for high-performance, low-power drives

SAN JOSE, California, September 21, 1999 – Palmchip Corporation today introduced a new family of four complete SOC (system-on-chip) IP (intellectual property) designs aimed at reducing the overall development time involved in building advanced disk drive systems. The new GreenLite™ II family of high integration, low power single-chip disk controllers includes the following members (a comparison chart is on page 4 of this release):

 
• GreenLite™ IID for high performance desktop system drives
• GreenLite™ IIP for microdrives and PC card drives
• GreenLite™ IIR for removable high-density and floppy disk drives
• GreenLite™ IIS for PC card and Compact Flash solid state drives

"Our new GreenLite™ II family serves designers needing single-chip solutions to achieve higher integration, lower power consumption, and smaller die sizes," said Jauher Zaidi, president and CEO of Palmchip. "Our SOC IP delivers all the digital circuitry required for complete disk drive controllers. This can cut months off a design cycle, dramatically reducing cost and improving time to market."

GreenLite™ Family Features

Each member of the new GreenLite™ II family features Palmchip's powerful second-generation, highly configurable memory subsystem and allows customers to specify their preferred microprocessor. Other features include on-chip instruction cache, an 8KB SRAM for time-critical 

code and variables, and a UART for system debug. An integrated patented ECC engine implements a Reed-Solomon algorithm with customizable symbol lengths and interleaving. A digital servo engine is highly configurable to support many servo data patterns, with auto error correction capability. An ID-FREE formatter incorporates a flexible defect FIFO buffer and high-speed read channel interface to maximize performance. Independent serial interfaces for programming motor, pre-amplifier and read channel devices are available, along with a variety of disk drive or solid state memory interfaces.

The GreenLite IID provides an ATA/IDE interface with support for Ultra-DMA 66 for high performance desktop PCs; the GreenLite IIR features a dual ATA/IDE/floppy interface for systems requiring floppy disks; GreenLite IIP features a PCMCIA interface with ATA passthrough operation for notebook PCs; and the GreenLite IIS offers PCMCIA and Compact Flash form factor interfaces for mobile solid state disk drives and rotating microdrives.

"The GreenLite™ II family is a good example of how Palmchip can create complete SOC solutions to suit specific applications," states Melissa Jones, vice president of marketing for Palmchip. "Each member of the family is configured from a powerful Palmchip microcontroller platform – what we call a FlexiSOC™ design. FlexiSOC™ designs allow us to build specialized solutions for mass storage and other applications very quickly. Using this methodology, we can help customers dramatically reduce time to market."

The CoreFrame™ Architecture

Underlying Palmchip's FlexiSOC™ methodology is its CoreFrame architecture. This architecture is a high-performance IP integration platform that allows functional blocks to be combined together with "plug and play" simplicity to reduce SOC development time. The technology allows fast porting of IP and software from Palmchip, the customer, or a variety of third-party CoreFrame™ DirectConnect partners. Its inherent flexibility allows customers to select their particular choice of processor and I/O, and to safeguard their own proprietary IP. 

The architecture is synthesis friendly and foundry independent. It is ideal for use in applications with low power requirements, such as mobile communications and other battery powered devices. The architecture is memory-centric rather than processor-centric. It features a shared memory access controller that is optimized for devices with high bandwidth data streams requiring extensive DMA (direct memory access), such as in mass storage and networking applications. Another key feature of the CoreFrame™ architecture is its channel-based structure that enables it to support popular bus architectures.

Availability and Pricing

The GreenLite™ II technology has been instantiated into multiple applications. Designs are delivered as Verilog source code. Co-verification and test benches are provided. Single-use and multiple-use licenses are available. Contact Palmchip directly for pricing information.

About Palmchip
Palmchip develops and licenses semiconductor IP (intellectual property) as complete SOC solutions or configurable subsystems. Palmchip also develops and licenses embedded firmware and supplies design services. The company provides Verilog source code, target optimized netlists, synthesis scripts, test vectors, and complete documentation. Target markets include mass storage, wireless communications, consumer portables, networking, Internet security, and office automation. Palmchip is privately held and has offices in San Jose, California and Loveland, Colorado. Palmchip is a member of the Virtual Socket Interface Alliance. Further information may be found at http://www.palmchip.com
 

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