Denali Software and Prism Circuits Prove DDR3 Controller-PHY Interoperability

Seamless Integration of DDR3/2 Combo PHY With Databahn Memory Controller Streamlines Memory Sub-System Design

SANTA CLARA, CA and SUNNYVALE, CA -- April 21, 2009 - Prism Circuits, Inc., a leading supplier of high-quality parallel and serial interconnect IP, and Denali Software, Inc., a world-leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced interoperability validation of Prism's DDR3/2 Combo PHY with Denali's Databahn Memory Controller. Prism's fully-integrated solution complies with the latest DFI specification and provides the physical layer (PHY) interface between the controller logic and DDR3 DRAM devices to achieve datarates up to 2133Mbps.

"Prism is well known in the industry for delivering high-performance PHY solutions," said David Lin, Vice President of Marketing at Denali Software, Inc. "This Prism DDR3/2 Combo PHY extends our ability to offer best-in-class, end-to-end memory interconnect solutions to meet the needs of our customers worldwide."

"Denali is the market leader in high-quality, high-performance DDR memory controllers," said Sundari Mitra, CEO of Prism Circuits. "Seamless interoperability between Prism's DDR3/2 Combo PHY and Denali's Databahn memory controllers ensures speedy time to market for our customers' chip designs."

Prism's DFI 2.1 compliant DDR3/2 Combo PHY product is available to chip designers using TSMC's 40G and 65GP processes. In addition, Prism's DDR3/2 Combo PHYs are also available at Fujitsu 65HP and 45HP processes. Prism's DDR3/2 Combo PHY solution is available in both wirebond and flipchip configurations. Offering a choice of 1.8V or 2.5V IO FETs, the DDR PHYs support datarates up to 2133Mbps. Denali's Databahn Memory Controller ships at the RTL level and is compatible with all of these vendor processes.

About the DFI Specification

The DDR PHY Interface (DFI) specification defines an interface protocol between memory controller logic and PHY interfaces, with a goal of reducing integration costs while enabling performance and data throughput efficiency. The protocol defines the signals, timing, and functionality required for efficient communication across the interface. The specification is designed to be used by developers of both memory controllers and PHY designs, but does not place any restrictions on the how the memory controller interfaces to the system design, or how the PHY interfaces to the DRAM devices. For more information about the DFI specification, its community, activities and how to participate, visit: www.ddr-phy.org.

About Denali Software

Denali Software, Inc. is a world-leading provider of electronic design automation (EDA) software and intellectual property (IP) for system-on-chip (SoC) design and verification. Denali delivers the industry's most trusted solutions for deploying USB, PCI Express, NAND Flash and DDR DRAM subsystems. Developers use Denali's EDA, IP and services to reduce risk and speed time-to-market for electronic system and chip design. Denali is headquartered in Sunnyvale, California and has offices around the world to serve the global electronics industry. More information about Denali, its products and services is available at www.denali.com.

About Prism Circuits, Inc.

Prism Circuits, a privately held company, is a leading supplier of high quality parallel and serial interconnect IP. Prism's silicon proven portfolio includes DDR3/2 Combo PHYs as well as SerDes IP that support datarates from SGMII (1.25Gbps) to CEI-11 (11.3Gbps). These also include XAUI (3.125Gbps and 6.25Gbps), USB 3.0 (5Gbps), PCI Express Gen1 (2.5Gbps) and Gen2 (5.0Gbps), SATA I, II, and III, and 10G KR. For more information please see http://www.prismcircuits.com