Arasan Chip Systems Announces highly integrated 10G Ethernet MAC IP Core

Arasan expands Ethernet IP portfolio with 10G Ethernet MAC IP Core   

San Jose, California - June 22, 2010 - Arasan Chip Systems, Inc. ("Arasan"), a leading provider of Total Semiconductor IP Solutions, announced the release of its 10 Gigabit Ethernet MAC IP core. 10 Gigabit (10G) Ethernet boosts network bandwidth, thereby enabling the delivery of next generation applications over a common Ethernet platform. This high quality IP expands Arasan's growing portfolio of Ethernet and Connectivity IP cores.

Arasan's 10 Gigabit Ethernet MAC IP Core is compliant with the IEEE 802.3-2008 standard and incorporates a powerful 64-bit scatter-gather DMA to optimize network stack performance. All of the key functions of the Ethernet protocol such as IPG checking, address filtering, FCS and PAD processing, packet error checking are done in hardware thereby minimizing the burden on the host processor.

Commenting on the release of this IP, Prakash Kamat, Vice-President of Engineering at Arasan said, "Networking ASIC and chipset designers can capitalize on the rising demand for 10G Ethernet deployments by using Arasan's highly optimized 10G Ethernet MAC IP core. Designers can rely on our extensive Ethernet protocol expertise to achieve success in integrating 10G Ethernet on their silicon."

With Service Providers and Enterprise IT managers standardizing on an Ethernet based network infrastructure, 10G Ethernet enables them to replace multiple networks while increasing the bandwidth and lowering operating costs. The higher bandwidth also enables Enterprise wide virtualization, resulting in more efficient use of compute resources. Designers of Host-bus adapters, server connectivity and advanced storage applications can offer robust chipsets using Arasan's proven 10G Ethernet MAC IP core.

Arasan's 10G Ethernet MAC IP core supports full-duplex operation at 10Gbps and all standard features such MDIO/MDC PHY management, MIB, SNMP, RMON network management. It supports MagicPacket and WakeonLAN to conserve power. The core also supports PAUSE frame management to throttle output based on network congestion. Arasan also offers two optional modules - a XAUI Interface module that extends the XGMII interface to a XAUI interface and an optional 64B/66B PCS module to interface with a 10G SerDes module.

 "10G Ethernet is increasingly being adopted as the technology that scales across LAN, MAN and WAN connectivity," said Somnath Viswanath, Product Marketing Manager at Arasan. "By integrating Arasan's proven 10G Ethernet MAC IP core, designers can offer chipsets that handle data and bandwidth intensive applications such as large corporate database access, enterprise data backup and HD media using a common Ethernet infrastructure".

Arasan provides a Total IP solution to enable the rapid integration of 10G Ethernet interface into chipsets and network processors. This solution consists of RTL code, verification IP, software stacks, hardware platforms for development and validation - all backed by our World-class customer support.

About Arasan

Enabling Technology Adoption through Total IP Solutions - The Bus Stops Here!

Arasan Chip Systems based in San Jose, CA, USA, is a world-leading supplier of SoC Intellectual Property Solutions with a successful 15 year track record. Arasan delivers technology-leading IP focused on Bus Interfaces such as MIPI, SDIO, USB, PCIe, Ethernet, and Flash Storage Solutions of NAND, eMMC, SD,  CF+, UFS and more, to the global electronics market.  Arasan's Total Solution Approach starts with Technology Consulting using our Domain Expertise and includes all the building blocks required for technology adoption- RTL IP cores, Analog Mixed Signal IP Cores, Verification IP,  Portable Software Drivers / Stacks, Protocol Test & Analyzers, HDK's,  and associated design services. Arasan Total IP Solution enables the rapid adoption of emerging technologies reducing our customer's time to market while minimizing risk and ensuring compliance to respective standards.