IP Cores, Inc. Ships Compression/Encryption Combo IP Core

IP Cores, Inc. Announces a New Family of Compression/Encryption IP Cores for Data Storage Applications.

Palo Alto, California -- July 5, 2010 -- IP Cores, Inc. has shipped  first member of its new high-speed lossless data compression / encryption IP core family.  

"Our new LXP2 family of IP cores supports lossless data compression with practically unlimited block size as well as AES-XTS encryption standardized by NIST," said Dmitri Varsanofiev, CTO of IP Cores. "Tight coupling between compression and encryption enables simple integration and low latency; both features beneficial for any high-speed storage application, including enterprise solid-state (flash) drives".

AES-XTS Encryption

XTS is a short name for “XEX-based Tweaked CodeBook mode (TCB) with CipherText Stealing (CTS)”. Ciphertext stealing provides support for sectors that are not multiples of  AES data block size, for example, 520-byte sectors common in the flash storage.

XTS-AES was originally standardized by the IEEE P1619 group. In January of 2010, NIST supported the XTS mode by issuing the Special Publication (SP) 800-38E; a recommendation for the XTS-AES mode of operation, as standardized by IEEE Std 1619-2007. Per SP 800-38E, "In the absence of authentication or access control, XTS-AES provides more protection than the other approved confidentiality-only modes against unauthorized manipulation of the encrypted data."

Lossless Compression

Lossless data compression is a class of data compression algorithms that allows the exact original data to be reconstructed from the compressed data.  Lossless compression is used when it is important that the original and the decompressed data be identical, or when no assumption can be made on whether certain deviation is uncritical. Typical applications include data storage and transmission.

LXP2 Family of  Cores

LXP2 implements the lossless compression and encryption algorithms on units of data (“blocks”). The core supports configurable maximum block sizes up to 16 megabytes (the limit imposed by the SP800-38E). The design is fully synchronous and available in multiple configurations varying in bus widths and throughput.

LZR1 can easily deliver few Gbps of throughput in both FPGA and ASIC implementations. The compression ratio greatly depends on the data and somewhat depends on the frames size; on typical file corpuses varies between 1.5 and 2.

LXP2 datasheet is available here.

About IP Cores, Inc.

IP Cores is a rapidly growing company in the field of security, error correction, and DSP IP cores. Founded in 2004, the company provides IP cores for communications and  storage fields, including AES-based ECB/CBC/OCB/CFB, AES-GCM and AES-XTS cores, flow-through AES/CCM cores with header parsing for IEEE 802.11 (WiFi), 802.16e (WiMAX), 802.15.3 (MBOA), 802.15.4 (Zigbee), public-key accelerators for RSA and elliptic curve cryptography (ECC), cryptographically secure pseudo-random number generators (CS PRNG), secure SHA and MD5 hashes, lossless data compression cores, low-latency fixed and floating-point FFT and  IFFT cores, as well as cyclic, Reed-Solomon, BCH and Viterbi decoder cores.