Dolphin Integration announces the availability of the HD-LP Panoply at 130 nm for reducing SoC area up to 20%

Meylan, France – July 23, 2010.  The release of this High Density and Low Power optimized Panoply of Silicon IPs is a windfall for Designers to improve the area of their SoCs up to 20% for the whole of logic with:

• The 6 track Standard Cell Library, HD-BTF
• The speed optimized Standard Cell Library, HS-BTF
• The Aura architecture for One Port and Two Ports Register Files from 128 bits up to 64 kbits
• Single Port and Dual Port RAMs Haumea from 16 kbits up to 512 kbits
• The Single Metal Programmable ROM Cassiopeia from 1kbit up to 1MBit
• Evaluation solutions to assess the performances of the Panoply at SoC level
• After-sale Application and Integration support to ensure the highest SoC density

To increase or just maintain their strength on the market, manufacturers of high density consumer and nomad devices must regularly offer more features to their end-users while offering competitive pricing. Because of this trend, finding the best compromise between low power and cost reduction is a significant challenge for Designers.

The HD-LP Panoply maximizes the RoI of any density and power optimized design:

• Depending on the instance capacity, the spRAM Haumea is up to 15% denser than contender’s solutions while ensuring 50% less dynamic power consumption
• Embedding the patent pending Access Strip, the dpRAM Haumea is up to 30% denser than traditional dpRAM
• Instances generated with the Cassiopeia architecture for ROM are up to 2 times smaller than alternative solutions
• The Aura architecture for Register Files is designed to be mixable in the logic blocks among the rows of the Standard Cell Library
• The Standard Cell Library HD-BTF is up to 30% denser and twice less consuming than a typical 9 track Standard Cell Library after P&R

Check up by yourself the performances of the HD-LP Panoply on your design:

• For memories, follow the link below to get access to the online generators ttp://www.dolphin.fr/flip/ragtime/013/ragtime_013_ram.html

• For Standard Cells, benchmark against any other standard cells library now is easy with the Sofia Benchmark and the Motu Uta public standard http://www.dolphin.fr/flip/sesame/benchmark/sesame_bench_registration.php

Contact us to take advantage of our suggested Application Schematics, Prescriptions and Consistency of Products for a power and density-optimized architecture: ragtime@dolphin.fr

About Dolphin Integration

Dolphin Integration is up to their charter as the most adaptive and lasting creator in the Microelectronics Design Industry to "enable mixed signal Systems-on-Chip". It stars a quality management stimulating reactivity for innovation as well as independence and partnerships with Foundries. Their current mission is to supply worldwide customers with fault-free, high-yield and reliable sets of CMOS Virtual Components. The strategy is to follow product launches with evolutions addressing future needs, emphasizing resilience to noise and drastic reductions of power-consumption at SoC level, thanks to their own missing EDA solutions enabling Integration Hardware Modeling (IHM) and Application Hardware Modeling (AHM) as well as early Power and Noise assessment, plus engineering assistance for Risk Control. For more information about Dolphin, visit: www.dolphin.fr/sesame