Sibridge Technologies & Axiom Design Automation Partner to Integrate Verification IPs with SystemVerilog

Integrates a large portfolio of Verification IPs with industry proven SystemVerilog Platform to provide unsurpassed flexibility for large regression farms

Santa Clara & Milpitas, California, May, 25 2011: Sibridge Technologies, a leading provider of Design and Verification IPs, with expertise in ASIC/SoC design & verification and Embedded solutions and Axiom Design Automation, provider of fastest path to verification closure for semiconductor design, today announced a partnership agreement that will offer customers an integrated solution for accelerating SoC design & verification. The partnership combines the state-of-the-art verification platform, portfolio of Verification IPs (VIP), EDA & Test and design services.

Sibridge’s large portfolio of Verification IP (VIP) for industry-standard interfaces including PCI Express Gen 1.1, 2.0, 3.0, Ethernet 10G/1G/100M/10M, USB 2.0/3.0, AMBA AHB/AXI and I2C are integrated with Axiom’s MPSim 5.0 to provide seamless verification. Axiom’s MPSim is industry proven high performance Verilog and SystemVerilog simulator with the most advanced integrated debugger. MPSim incorporates SystemVerilog and OpenVera testbench automation with SVA and coverage analysis in a single kernel architecture for maximum performance and throughput.

“The partnership will enable our mutual customer with comprehensive verification solutions to accelerate silicon success by reducing the verification time”, said Rajesh Shah, CEO, Sibridge Technologies. “Customer can now rely on the very best VIP and industry proven EDA tools to streamline their chip design and verification process with an added advantage of comprehensive support and integration services” added Rajesh Shah.

“The partnership perfectly fits our strategy to offer the most comprehensive and integrated verification platform to our customers”, stated Badru Agarwala, President and CEO of Axiom Design Automation. “Due to its superior performance, productivity and predictability capabilities, MPSim is fast becoming the verification platform of choice for verification of complex SoCs and many of our customers have very large verification farms based on MPSim for regression testing. Now integrated with a large portfolio of complex verification IPs, Axiom’s flexible business model offers our customers unsurpassed flexibility in developing and deploying the best price performance verification and regression environment for complex designs”.

About Sibridge Verification IP

Sibridge offers a large portfolio of verification IPs, comprising of PCI Express Gen 1.1, 2.0, 3.0, Ethernet 10G/1G/100M/10M, USB 2.0/3.0, AMBA3/4 AXI, AMBA2 AHB/APB, I2C, UART and SPI. These VIPs provide a rich set of configuration parameters for controlling VIP functionality along with built-in coverage to facilitate verification progress analysis.

About Sibridge Technologies

Sibridge Technologies provides innovative value added solutions for design, verification, and embedded systems development to worldwide semiconductors and electronic product companies. The company offers a unique blend of three critical components in the development of SoCs: design and verification IP portfolios; strong chip design, integration, and verification expertise; embedded systems hardware & software design and validation for streaming media, wireless, and networking applications. The company has design centers in Ahmedabad, India and Santa Clara, USA. For more information please contact info@sibridgetech.com or visit http://www.sibridgetech.com

About Axiom

Axiom Design Automation is a company focused on providing the best-in-class verification platform to address the growing complexity of today’s FPGAs, ICs, SOCs and systems. Axiom’s flagship product, MPSim is the state-of-the-art, industry proven high performance SystemVerilog simulator integrated with an advanced debugger, compiled testbench automation, multiple clock domain verification and comprehensive coverage analysis for quick verification closure. MPSim incorporates SystemVerilog and OpenVera testbench automation with SVA and coverage analysis in single kernel architecture for maximum performance. MPSim is fully compliant with industry standards such as VMM, OVM, UVM, UPF, etc. For more information please visit www.axiom-da.com.