Jasper to Release First of Its Kind System-Level Verification IP (VIP) for ARM ACE-based SoCs

Jasper Solutions Used Extensively to Validate the High Quality and Robustness of ACE Specification

Mountain View, CA, June 07, 2011.  Jasper Design Automation, the leading provider of verification solutions based on formal technology, today announced the availability of its suite of system-level VIP for AMBA 4 ACE-based SoCs.  The VIP is the first of its kind for the ACE specification and was a direct result of the tight collaboration between ARM and Jasper for validating the quality and robustness of the specification.

“Our goal was to support a specification to improve cache coherency for complex multicore SoCs and so maximize performance and power efficiency,” said Michael Dimelow, Director of Marketing, Processor Division, ARM. “We recognize that the enormous complexity of these challenges requires a suitable verification platform.   The release of Jasper’s System-Level Verification IP for AMBA 4 ACE provides customers with an advanced solution for multicore SoC design.”

The collaboration with ARM not only validated the specification, but also resulted in certification of Jasper’s system-level VIP for ACE. Jasper’s VIP for ACE addresses complex system-level issues such as absence of deadlocks and cache coherency.  Among the features, is a new query-able ACE model that was developed in partnership by Jasper and ARM to enable end users to comprehend the ACE specification and answer system-level design questions.  An ACE architecture executable model can be used to help customers verify compliance to the ACE protocol as they extend their architecture to include private protocols and IP.

“We are proud to be the first source of certified VIP for ACE and are excited to know that our technology will go a long way in reducing the risks our customers take in their design and verification.” Said Kathryn Kranen, President and CEO of Jasper Design Automation. “The close work we did with ARM has enabled a verification ecosystem that can target the most important verification challenges.  Problems that were previously intractable are now able to be resolved.”

Availability AXI4 bus VIP and ACE protocol checkers are immediately available.  Each is delivered as an option to Jasper’s Intelligent ProofKits.  The Jasper VIP is available for use in simulation or in formal verification with Jasper solutions.

About Jasper Design Automation

Jasper delivers industry-leading EDA software solutions for semiconductor design, verification, and reuse, based on the state-of-the-art formal technology. Customers include worldwide leaders in wireless, consumer, computing, and networking electronics, with over 150 successful chip deployments.  Jasper, headquartered in Mountain View, California, is privately held, with offices and distributors in North America, South America, Europe, and Asia.  Visit www.jasper-da.com to reduce risks; increase design, verification and reuse productivity; and accelerate time to market.