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Dolphin Integration launches a 65 nm compiler for Dual Port Register Files reaching the highest densityGrenoble, France and Netanya, Israel – September 12, 2011. The ERIS architecture for Dual Port Register File compiler, already available in 130 nm, is now adapted to the 65 nm and its shrunk version at 55 nm. Specifically suited for mainstream applications ranging from embedded microcontrollers to high-density consumer and portable devices, the ERIS generator is cost-optimized. It meanwhile provides the smallest power consumption, leaving far behind the competing generators currently available. As an example, one instance of 416 bits achieves a power consumption as low as 2.83 uW for a density of 0.0052 mm2 in 65 nm. Such performances are due to its unique architecture optimizing the periphery area for outstanding area gain. About the benefits of DpRFile ERIS compiler in 65 nm LP
For more information, feel free to download DpRFile ERIS presentation sheet or to contact Elsa BERNARD-MOULIN: ragtime@dolphin-ip.com About Dolphin Integration Dolphin Integration is up to their charter as the most adaptive creator in the Microelectronics Design Industry to "enable mixed signal Systems-on-Chip". It stars a quality management stimulating reactivity for innovation and foundry independence. Their current mission is to supply worldwide customers with fault-free, high-yield and reliable sets of CMOS Virtual Components, resilient to noise and drastic for low power-consumption, together with engineering assistance and product evolutions customized to their needs.
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