Toshiba to license MeP-based MPEG-2 codec

Toshiba to license MeP-based MPEG-2 codec
By Yoshiko Hara, EE Times
May 15, 2002 (5:04 p.m. EST)
URL: http://www.eetimes.com/story/OEG20020515S0040

TOKYO—Toshiba Corp. has developed a single-chip MPEG-2 MP@ML codec based on its configurable Media Embedded Processor (MeP) architecture, which the company presented in detail at the IEEE Custom Integrated Circuits Conference this week in Orlando, Fla.

MeP is a configurable RISC processor architecture for embedded applications. A customized MeP processor core with extensions forms a Media Module. By integrating several MeP modules with additional intellectual property, Toshiba says, it's possible to quickly design application-specific systems-on-chip.

The single-chip MPEG-2 Main Profile at Main Level codec integrates 3.8 million gates on a 72 mm² die using an 0.18-micron process. Running off a 3.3-volt power supply (1.5 V internally), the codec uses a 150-MHz system clock and consumes 1.5 watts to realize simultaneous digital video and audio encoding and decodi ng in standard definition (MP@ML) and video and audio decoding in high definition (MP@HL).

The MPEG-2 codec packs six Media Modules for bit stream mux/demux, audio and video encoding and decoding, motion estimation, video pre- and postprocessing, and general control. These modules are connected to the single main bus. A user custom-instruction unit, DSP, hardware engine and VLIW coprocessor are defined as MeP extension options. The audio module houses the very long instruction word coprocessor, while the video encoding and decoding modules include the digital signal processor, hardware engine and user custom-instruction unit.

"The MPEG-2 codec is one of the most complex applications of MeP," said Masataka Matsui, senior manager of the digital media system-on-chip department at Toshiba's SoC Research & Development Center. "Designing the MPEG-2 codec LSI was the first target [Toshiba had] when we started developing the MeP architecture."

Reuse environment

Toshiba has ample MPEG know-how accumulated from past projects. But no reuse environment was ready, said Shunichi Ishiwata, a digital multimedia specialist in the company's LSI development group. The MPEG-2 codec, therefore, served as a driving force for preparing the reuse environment for the MeP architecture.

"It is easier to reuse software than hardware, so I tried to keep the use of hardware as [minimal] as possible," said Ishiwata. "In SoC design, I've been having the impression that engineers tend to lean too much on hardware. But I made full use of software because an LSI does not have high performance unless software is fully made use of."

LSI Logic Corp. (Milpitas, Calif.) announced a single-chip MPEG-2 codec, dubbed DMN-8600, in January, demonstrated it at the Winter Consumer Electronics Show and is now establishing volume production.

Toshiba, however, "won't supply the chip itself to system customers," said Matsui. In stead, it intends to build a business around MeP, licensing the architecture and providing development tools and pieces of IP. Toshiba has already built demo systems with the one-chip codec to show off the architecture.