Agere unveils single-chip Sonet framers, ADM SoC

Agere unveils single-chip Sonet framers, ADM SoC
By EE Times
October 19, 2001 (1:03 p.m. EST)
URL: http://www.eetimes.com/story/OEG20011019S0089

Allentown, Pa. - Agere Systems has introduced two single-chip synchronous optical network/synchronous digi-tal hierarchy (Sonet/SDH) framers and one of the first add-drop multiplexer (ADM) system-on-chip devices.

The TDAT042G5LT and TDAT04622LT integrate time-division-multiplexed (TDM) and data-mapping framers for asynchronous transfer mode (ATM), Ethernet over Sonet (EoS) and packet-over-Sonet (PoS) onto a single chip for next-generation metro-area optical networks and third-generation (3G) wireless infrastructure.

Both devices are designed to map nearly all data and TDM traffic onto Sonet/SDH frames to improve cost-effectiveness and time-to-market for network equipment vendors. With the framers, a single circuit board can interface to multiple-rate networks and multiple data rates, including OC-48, OC-12 and OC-3. The benefits of such interfacing include greater flexibility, reduced equipment size and lower component counts.

< P> The devices serve as framing engines for EoS and Level 2 protocols, such as high-level data link control (HDLC), ATM and point-to-point (PPP) protocol. They target lower-cost network-access products and applications such as digital subscriber line access multiplexers (DSLAMs), 3G wireless basestations, routers, voice gateways and traffic-aggregation systems.

The TDAT042G5LT addresses 2.5-Gbit/second (OC-48) data rates and provides a single OC-48, quad-OC-12 or quad-OC-3 interface.

The TDAT04622LT targets 622-Mbit/s (OC-12) applications and provides a single OC-12 or a quad-OC-3 interface. Both devices are in production. They come in 680-ball plastic ball-grid array packages and are priced below $100 in 10,000-piece volumes.

The TADMVC2G5 is a single-chip programmable Sonet/SDH framer solution for OC-3 to OC-48c optical networks. It integrates an STS-1 granularity cross-connect, a packet-cell data engine and a pointer processor that supports virtual concatenation (VC) and generic f raming procedure technologies. Those features enable generalized mapping of variable-length, multiprotocol packets as well as flexible data transport over Sonet networks, for lower system costs and increased flexibility and efficiency.

Brian Schreder, Agere's director of marketing, said that the device provides an SoC solution for ADM functionality in PPP or ring-optical networks, and it addresses the merging of TDM and data networks within a single device.

Virtual concatenation extends Sonet transport efficiency by allowing any number of STS-1 channels to be grouped for transporting data streams, regardless of the type of data packet being transported. A generic framing procedure allows service providers to avoid PoS and other overhead-intensive, flag-based adaptation schemes for Internet Protocol router interconnection over wide-area networks, thus making it easier for providers to perform switching tasks.

"Service providers need an efficient method of supporting multiple-transport protocols," said Schreder. "For example, transporting a Gigabit Ethernet signal over Sonet via a contiguously concatenated STS-48c channel results in a 42 percent bandwidth efficiency. With VC, we can use 95 percent of the transport channel for data applications and the remaining six STS-1 channels for voice applications. Service pro-viders will also be able to supply bandwidth to meet specific application transport requirements."

The ADM chip is designed for OC-48c multiprotocol and ATM switches, routers, aggregation equipment, dense wavelength-division multiplexing equipment, voice gateways, next-generation DSLAMs and 3G wireless infrastructure applications.

Samples are available now and production is scheduled to begin sometime during the first quarter. The chip is packaged in a 600-ball LBGA and runs on 7.5 watts. It is priced at $825 in 1,000-piece quantities.

Call (800) 372-2447 or (610) 712-5130

www.agere.com

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