May 11, 2015 -- Sercos International announced the availability of the Sercos III IP Core for Xilinx 7 series FPGAs and devices of the Zynq SoC family. The IP core is available for Sercos III master and slave controllers (SERCON100M/S) for automation devices. It includes all hardware functions, such as timing, synchronization and processing of cyclic and non-cyclic data on the basis of two integrated Ethernet MACs. Sercos III master and slave devices can be implemented as a single chip solution using either Xilinx Artix®-7 FPGAs, other FPGAs of the 7 series or Zynq SoC devices, which integrate an ARM® dual-core Cortex™-A9 processor.
"The on-going use of the flexible and continually developing FPGA technology brings significant cost, performance and flexibility benefits to the Sercos community," said Peter Lutz, Managing Director of Sercos International e.V.
Detailed documentation on the IP core, reference designs and example Ethernet interface diagrams are available from Sercos International (www.sercos.org). Technical support and customer-specific design services are provided by Cannon-Automata, Ried/Germany and Caronno, Pertusella/Italy (www.automataweb.com).
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