IP Cores, Inc. Announces an Update for Its True Random IP Core

IP Cores, Inc. announces a release of the Revision 2.0 of its true random IP core

PALO ALTO, Calif. -- August 21, 2018 -- IP Cores, Inc., California, USA (http://www.ipcores.com) had announced modifications to its true random number generator IP core, TRNG1.

“Our true random generator IP cores are in high demand among ASIC and FPGA designers looking for a non-deterministic random bit generator (NRBG) for use in cryptographic applications per the NIST SP800-90B document,” said Dmitri Varsanofiev, CTO of IP Cores, Inc. “Revision 2.0 introduces features to simplify the FIPS-140 certification of the customer’s system with TRNG1 core. Our TRNG1 customers that have an active maintenance program can obtain the revision 2.0 free of charge”.

True Random Number Generators

Hardware True Random Number Generators (TRNG, see https://en.wikipedia.org/wiki/Hardware_random_number_generator) are critical security blocks typically utilized to generate random numbers for secret cryptographic keys as well as seeds for pseudo-random number generators. A good-quality random number generator is essential for security, since generating the keys from a poor random source will significantly reduce the entropy of the long keys and might allow a brute-force attack on the seed used to generate the key. A typical embedded application usually does not have access to high-quality randomness sources, so a designer of a System-on-a-Chip (SoC) targeting such application might want to instantiate a true-random source on the chip.

Many TRNG designs rely exclusively on physical features (ring oscillators or metastability) that require awareness and caution from the back-end designer doing placement and routing. IP cores, Inc. in its TRNG1 design has avoided the potential sources of these problems thus allowing the back-end processing with little or no extra effort spent on TRNG1. Innovative design of the entropy source requires practically no special handling during the physical design stages. As an example, a typical FPGA instantiation of the TRNG1 requires no special scripts or tool configuration whatsoever.

Additional information about TRNG1 can be found on the IP Cores, Inc. web site, http://ipcores.com/True_Random_Generator_TRNG_IP_core.htm

NIST SP800-90 Documents

Random number generation is covered by multiple standards, with most popular being AIS 20/31 and NIST SP 800-90. The original SP 800-90 publications had been replaced by the new SP 800-90Ar1 (https://csrc.nist.gov/publications/detail/sp/800-90a/rev-1/final), SP 800-90B (https://csrc.nist.gov/publications/detail/sp/800-90b/final) and SP 800-90C documents (https://csrc.nist.gov/publications/detail/sp/800-90c/draft).

About IP Cores, Inc.

IP Cores is a rapidly growing California company in the field of security, error correction, and DSP IP cores. Founded in 2004, the company provides hardware IP cores for communications and storage fields, including AES-based ECB/CBC/OCB/CFB, AES-GCM and AES-XTS cores, MACsec 802.1AE, IPsec and SSL/TLS protocol processors, flow-through AES/CCM cores with header parsing for IEEE 802.11 (WiFi), 802.16e (WiMAX), 802.15.3 (MBOA), 802.15.4 (Zigbee), public-key accelerators for RSA and elliptic curve cryptography (ECC), true random number generators (TRNG, NRBG), cryptographically secure pseudo-random number generators (CS PRNG, DRBG), secure SHA and MD5 cryptographic hashes, lossless data compression cores, low-latency fixed and floating-point FFT and IFFT cores, as well as cyclic, Reed-Solomon, LDPC, BCH and Viterbi forward error correction (FEC) decoder cores.