Synopsys Demonstrates Industry's First PCI Express 5.0 IP Interoperability with Intel's Future Xeon Scalable Processor

Successful Interoperability Enables Low-Risk Integration and Broad Adoption of the PCIe 5.0 Interface in High-Performance Computing SoCs

MOUNTAIN VIEW, Calif., Oct. 13, 2020 -- Synopsys, Inc. (Nasdaq: SNPS) today announced its collaboration with Intel to achieve successful system-level interoperability between the Synopsys DesignWare Controller and PHY IP for PCI Express 5.0 and future Intel Xeon Scalable processors (codename Sapphire Rapids). The full-system interoperability, a key milestone in Synopsys and Intel's ongoing collaboration, enables the ecosystem to confidently use the companies' proven technologies to accelerate development of their PCIe 5.0-based products in high-performance computing and AI applications. The DesignWare IP for PCI Express 5.0 has been licensed over a hundred times by customers across all key market segments, delivering the lowest latency and highest throughput IP compared to other solutions in the industry.

"Synopsys continues to collaborate with industry leaders like Intel to deliver high-quality IP that help designers address the bandwidth, power, area, and latency demands for the new era of high-performance computing systems," said John Koeter, senior vice president of marketing and strategy for IP at Synopsys. "Achieving successful interoperability between Synopsys' DesignWare IP for PCIe 5.0 and Intel Xeon Scalable processors validates that the IP functions as intended with Intel's industry-standard PCIe 5.0 products, accelerating the path to first-silicon success with less risk."

"The growth of high-performance computing applications converged with AI workloads requires innovative data connectivity and processing technologies that deliver low latency and fast speeds," said Jim Pappas, Director of Technology Initiatives at Intel. "We are pleased to collaborate with Synopsys, a leading provider of PCIe IP, to enable the ecosystem and ensure the widely adopted DesignWare IP for PCI Express 5.0 is interoperable with our future CPUs in order to enable the billions of PCIe-enabled products in the market."

Availability and Additional Resources

The DesignWare Controller, PHY, and Verification IP for PCIe 5.0 in a wide range of FinFET processes from 16-nm to 5-nm is available now.

For more information, visit the DesignWare IP for PCIe 5.0 web page.

About DesignWare IP

Synopsys is a leading provider of high-quality, silicon-proven IP solutions for SoC designs. The broad DesignWare IP portfolio includes logic libraries, embedded memories, embedded test, analog IP, wired and wireless interface IP, security IP, embedded processors, and subsystems. To accelerate prototyping, software development and integration of IP into SoCs, Synopsys' IP Accelerated initiative offers IP prototyping kits, IP software development kits, and IP subsystems. Synopsys' extensive investment in IP quality, comprehensive technical support, and robust IP development methodology enable designers to reduce integration risk and accelerate time-to-market. For more information on DesignWare IP, visit https://www.synopsys.com/designware.

About Synopsys

Synopsys, Inc. (Nasdaq: SNPS) is the Silicon to Software^™ partner for innovative companies developing the electronic products and software applications we rely on every day. As the world's 15^th largest software company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP and is also growing its leadership in software security and quality solutions. Whether you're a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing applications that require the highest security and quality, Synopsys has the solutions needed to deliver innovative, high-quality, secure products. Learn more at www.synopsys.com.