PCIe 5.0 & PCIe 4.0 PHYs and Controller IP Cores are available for immediate licensing to maximize your Interface speed for complex SoCs

December 20, 2021 – T2M-^IP, the global independent semiconductor IP Cores & Technology provider, is pleased to announce the immediate availability of PCIe Gen5 and PCIe Gen4 PHY IP Cores with matching Controller IP cores available in major Fabs and Process nodes. The entire solution is Silicon and Production Proven in various end application SoCs.

The Peripheral Component Interconnect Express (PCIe) Gen5 and Gen4 PHY IP cores were designed and tested to exceed PCI-SIG’s compliance spec in jitter tolerance and insertion loss and proved that both PCIe Gen5 and PCIe Gen4 can achieve lower power consumption due to additional PLL control, reference clock control, and embedded power gating control. The low power mode settings are fully configurable enabling the performance of the IP core to be tuned across various application scenarios to achieve application specific power consumption considerations. Both IP core come with x4 physical lane width and support for dual-port PLL with LC tanks enabling parallel interface of 16/32- bit (Gen4/5)

The PCIe 5.0 Serdes PHY IP core is compliant with PCIe 5.0 Base Specification with PIPE 5.1. It supports data transfer rate of 2.5 GT/s, 5.0 GT/s, 8.0 GT/s, 16.0 GT/s and 32GT/s. The PCIe Gen5 PHY IP core also supports SSC for EMI reduction with 3-tap FFE for TX preset. With a inbuilt EYE-monitor and EYE checker makes it highly controllable with a low power consumption in accordance with operating Voltage of 0.8V and 1.2V and additional features such as Auto power saving for short reach.

The PCIe 4.0 Serdes PHY IP core compliant with PCIe 4.0 Base Specification with PIPE 4.4. It supports data transfer rates of 2.5 GT/s, 5.0 GT/s, 8.0 GT/s and 16.0 GT/s with an input reference clock of 100MHz. It also supports parallel interface data clock of 62.5 MHz, 125 MHz, and 250 MHz and 500MHz. The PCIe Gen4 PHY IP core supports low power operation with configurable setting in power state P1/P2/L1 and operating voltage of 0.8V and 1.2V. The IP Core also provides robust testability by low-cost Build-In-Self-Test (BIST) via near-end analog and external loopback interface as well as far-end.

High-performance PCIe Gen5 Controller IP Core & PCIe Gen 4 Controller IP Core are fully backward compatible with PIPE interface including full link speed and width negotiation up to 8 Lanes. These controllers are also available independently or pre-integrated with the PHYs as a fully validated and integrated solution. The PCIe PHYs can also be licensed separately and integrated with third-party controller solutions.

In addition to PCIe 5.0 and PCIe 4.0 PHYs and Controller IP Cores, T2M ‘s broad silicon Interface IP Core Portfolio includes USB, HDMI, Display Port, MIPI, DDR, 10/100/1000 Ethernet, V by One, programmable SerDes, Serial ATA and many more Controllers with matching PHYs, available in major Fabs in process geometries as small as 7nm. They can also be ported to other foundries and leading-edge processes nodes on request.

Availability

These IP cores are available for immediate licensing stand alone or with the matching Controllers. For more information on licensing options and pricing please drop a request / mailto: contact"at"t-2-m.com

About T2M

T2M^IP is the global independent semiconductor technology provider, supplying complex IP Cores, software, KGD and disruptive technologies enabling accelerated development of your storage, servers, networking, communications, TV, STB, Satellite and add-on PC cards SoCs. For more information, please visit: www.t-2-m.com