Andes Announces the N25F-SE Processor, the World First RISC-V CPU IP with ISO 26262 Full Compliance

Systematic failures and random hardware failures can be mitigated by development process and safety designs of the safety-enhanced N25F-SE

HSINCHU, TAIWAN – October 17, 2022 – Andes Technology, a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and founding premier member of RISC-V International, today announces its safety-enhanced AndesCore® N25F-SE is the first RISC-V CPU IP certified to be fully compliant with ISO 26262 functional safety standards for the development of automotive applications. SGS-TÜV Saar GmbH, an independent functional safety certification body, has assessed and completed product audit process for N25F-SE with achieved functional safety for ASIL B (Automotive Safety Integrity Level B) applications, according to all applicable ISO 26262 series of standards including Parts 2, 4, 5, 8 and 9.

AndesCore® N25F-SE. The N25F-SE is a 32-bit RISC-V CPU core that supports standard IMACFD extensions, including efficient integer instructions and single/double precision floating point instructions. It incorporates the Andes V5 extension instructions to further boost performance and reduce code size. The efficient 5-stage pipeline of the N25F-SE provides a good balance of high operating frequency and compact design. Its flexible interfaces greatly simplify SoC designs. Like its sought-after cousin the N25F, the N25F-SE comes with rich configurable options, all of which are fully certified, and thus SoC design teams are not limited by one fixed CPU configuration when offering automotive solutions.

ISO 26262 and ASIL-B Applications. ISO 26262 defines functional safety as the “absence of unreasonable risk due to hazards caused by malfunctioning behavior of electrical/electronic systems”. To enforce functional safety with a reasonable cost structure, proper safety measures for desired ASIL levels should be applied, from the least stringent ASIL A to the most stringent ASIL D. Examples of electronic systems where ASIL B is sufficient are dashboard, in-car monitoring, keyless entry, lighting control, tire pressure monitoring, vision ADAS, and window control. Either to incorporate new electronic systems on board, or to upgrade existing ones without ISO 26262 compliance, the N25F-SE is well suited for the wide range of applications requiring ASIL B compliance.

Leader of RISC-V Functional Safety. “Andes is the first RISC-V CPU vendor certified, for the development process of automotive processor cores, to be compliant with ISO 26262 standards up to ASIL D in 2020. With the certified development process in place, we formally started our functional safety roadmap to deliver at least one ISO 26262 compliant core every year to cover all segments of performance and features,” said Dr. Charlie Su, President and CTO of Andes Technology. “Andes has developed a wide range of AndesCore® processors, from driving cost sensitive MCUs to accelerating datacenter AI/ML computations. We are excited to announce our first safety-enhanced AndesCore® the N25F-SE based on the most popular and mature CPU IP family, the 25-series.”

ISO 26262 Full Compliance. The ASIL B fully compliant N25F-SE was developed under considerations on all applicable requirements of ISO 26262 standards by defining tailored safety activities with solid rationales, from the fundamental specification, analysis, and design to verification and many more. It comes with the Safety Package which includes Safety manual, Safety analysis report (FMEDA and more), and Development Interface Outline. Together, the N25F-SE and its Safety Package offer an effective, efficient, and flexible automotive solution. It greatly reduces the time for SoC design teams to certify their ISO 26262 compliant SoCs. In comparison, an ASIL B “ready” solution is without certifying all required ISO 26262 Parts (2, 4, 5, 8 and 9) and thus provides incomplete support for the SoC’s certification; as a result, SoC design teams must go through all the work the CPU IP vendors are supposed to do. In addition, the N25F-SE helps reduce the cost and power consumption for SoCs requiring only an ASIL B processor IP without forcing them to use a double-sized dual-core lock-step solution with ASIL D. “As the only public RISC-V CPU IP company and a leader in the RISC-V ecosystem, we want to raise the awareness of the importance of ISO 26262 full compliance.” Dr. Su stressed.

Cidana . “Consumer experience is shaping expectations for In-Vehicle Infotainment (IVI) systems. It is one of the segments evolving rapidly in the automotive industry. Cidana offers the optimized LC3+ codec and makes it available on Andes ISO 26262 compliance platform. Other mainstream audio codecs can be supported based on the required performance,” said Chinn Chin, the Chief Executive Officer of Cidana. “We are looking forward to collaborating with Andes and bringing the Cidana solutions to automotive SoCs powered by the N25F-SE.”

Green Hills Software . “We are pleased to expand our production-ready automotive safety solutions to support the safety-certified AndesCore® 25-Series RISC-V IP core family from the technology leader, Andes Technology,” said Dan Mender, Vice President, Business Development, Green Hills Software. “This combined hardware-software solution for the AndesCore N25F-SE gives SoC providers a valuable head-start in offering integrated and optimized production-proven platforms for next-generation vehicle ECUs that require the highest performance and lowest power, with advanced tools that reduce their customers’ time to market and development costs.”

IAR Systems . “RISC-V is being adopted at a remarkable speed in applications from the edge to the cloud and now it is entering the automotive market. IAR Systems support the mature and popular Andes RISC-V 25-series processors since its release a few years back in the IAR Embedded Workbench for RISC-V, Functional Safety edition. We are glad to learn that Andes N25F-SE has been certified for full ISO 26262 compliance,” said Rafael Taubinger, Sr. Product Marketing Manager at IAR Systems. “We are looking forward to extending our collaboration with Andes to support its Safety Enhanced processors starting from the N25F-SE enabling our mutual customers to speed up the path to using RISC-V in automotive safety-critical applications.”

Parasoft. “We would sincerely congrats on Andes Technology's N25F-SE been certified to the ISO 26262 functional safety standard,” said Yue Liu, the President of Parasoft Greater China. "Andes is a leading provider of RISC-V processors, and PARASOFT, a solution provider that helps enterprises deliver defect-free software, is pleased to partner with Andes to further deliver RISC-V ecosystem solutions to our customers. I am confident that we will be able to provide a complete suite of testing solutions for the automotive safety lifecycle in the near future, helping customers improve their ability to develop and deliver high quality software.”

Virtual Open Systems . “At Virtual Open Systems we are working with Andes to enable hypervisor-less mixed criticality virtualization supporting concurrent execution of a certified real time operating system (OS) with a general purpose OS using our VOSySmonitoRV , a low level firmware developed with ASIL certification in mind," said Daniel Raho, Virtual Open Systems SAS CEO. "We are excited to extend VOSySmonitoRV with support for Andes Safety Enhanced processors starting from the N25F-SE.”

The AndesCore® N25F-SE is available for licensing now. Over half of a dozen leading SoC companies are already developing in-vehicle applications with the N25F-SE. Following the N25F-SE, the D25F-SE with DSP/SIMD extension and Bit Manipulation extension is expected to be available in early 2023.

About Andes Technology

Seventeen years in business and a Founding Premier member of RISC-V International, Andes (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) is a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Andes’ fifth-generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, Vector, Linux, superscalar, and/or multicore capabilities. The annual volume of Andes-Embedded SoCs has exceeded 3 billion since 2021 and continues to rise. In the end of 2021, the cumulative volume of Andes-Embedded™ SoCs has surpassed 10 billion. For more information, please visit https://www.andestech.com.