Elevate the performance of your Automotive Application by integrating the IP cores of a 14-bit wideband Time-Interleaved Pipeline Data Converters

March 11, 2024 – T2M^IP, the global independent semiconductor IP Cores provider & Technology experts, is pleased to announce the availability of its partner’s silicon and production-proven 14-bit Wideband Time-Interleaved Pipeline ADC IP cores supporting 4.32 Gsps sampling speed in 28nm FDSOI process with complete source-code delivery and full modification rights and unlimited usage.

Automotive applications, including sensors and various components, require a high sampling rate to minimize data transfer latency and operate in real-time. This is particularly crucial for enhancing the performance of automotive technologies such as Lidar, which necessitates an ultra-high sampling rate for Advanced Driver-Assistance Systems (ADAS) to ensure maximum safety and reliability.

Derived from a production chipset, the 14-bit, 4.32Gsps Pipeline ADC IP Cores play a pivotal role in supporting these applications. They boast a 60dB Signal to Noise Ratio (SNR) and cover a broad input frequency range from 54MHz to 1.7GHz. This versatility makes them suitable for diverse applications, spanning Automotive, Microcontrollers, High-speed Set-Top Boxes (STB), Wi-Fi, Radar, and 5G technologies.

The ADC IP Cores incorporate two internal power supply regulators (LDO) for the analog part. These include a 1.1v LDO with an external decoupling capacitor to achieve a high-power rejection ratio and a 1.5v LDO with an internal capacitor for the input buffer and biasing. The digital part is powered by an external 1.0V source.

A mixed-signal system, the Pipeline ADC IP Cores consist of essential components such as a sample and hold amplifier (SHA), multiplying digital-to-analog converter (MDAC), bandgap voltage reference, comparator, switch-capacitor circuits, and biasing circuits. These components are interconnected to establish a link between system-level and circuit-level specifications. This design flow ensures that when overall ADC IP Cores specifications are provided, including resolution, sampling rate, voltage supply, and input signal range, all sub-block circuitry specifications are met.

The structure of a pipeline ADC IP Cores comprises several consecutive stages. The first stage, with a differential structure, evaluates the most significant bit (MSB) value, conditions the signal, and passes it to the subsequent stage for MSB-1 conversion. Each stage operates concurrently with others, contributing to the overall efficiency of the system.

T2M’s broad Wireless IP cores also include Bluetooth Dual mode v5.2 RF Transceiver IP Cores in 22nm ULL, BLE v5.2 / 15.4 (0.5mm2) RF Transceiver IP Cores in 40/55nm, NB-IoT/Cat M UE RF Transceiver IP Cores in 40ULP, Sub6 GHz RF Transceiver IP Cores, all can pe ported to other nodes and foundries as per the customer requirements.

Availability: These Analog Data convertors’ IP cores are available for immediate licensing. For further information on licensing options and pricing please drop a request at: contact.

About T2M: T2M-IP is the global independent semiconductor technology expert, supplying complex semiconductor IP Cores, Software, KGD, and disruptive technologies enabling accelerated development of your Wearables, IOT, Communications, Storage, Servers, Networking, TV, STB, and Satellite SoCs. For more information, please visit: www.t-2-m.com