Tensilica Eases Creation of Instruction Extensions For Xtensa Configurable Processors

Update: Cadence Completes Acquisition of Tensilica (Apr 24, 2013)

TIE Language Enhancements Provide Faster, Higher-Level Design Method to Boost SOC Performance

SANTA CLARA, Calif., June 16, 2003 – Tensilica, Inc. the leading supplier of configurable and extensible microprocessor cores, today announced a major step forward in the ability to quickly add new instructions to its Xtensa configurable processor. Now designers can specify new instructions at a much more abstract level. This new capability will make it much easier for system-on-chip (SOC) designers to experiment with different Xtensa processor configurations using the Xtensa Xplorer development environment, also introduced today.

"By allowing SOC designers to describe new instructions at an even higher level of abstraction, we're making them more productive by enabling faster and more thorough trade-off analysis," said Bernie Rosenthal, Sr. Vice President of Sales and Marketing at Tensilica. "Now, in an afternoon, engineers can test out ideas that would take months to implement with competing configurable processors. Additionally, they can be assured that the software development tool chain matches all modifications made to the hardware."

The new capabilities extend the Tensilica Instruction Extension (TIE) language with a higher-level syntax that describes a potential new instruction without first needing to explicitly define details such as opcode encoding or operand encoding, and without fully specifying the detail of the functional implementation or the details of user-defined register files and state variables. Tensilica's TIE Compiler, a desktop development tool for creating optimized Xtensa processors, can automatically determine the optimal instruction encodings and implementation in minutes using a process that "maps" the abstract instruction definition into a detailed implementation description.

Designers can use these new capabilities to quickly evaluate whether alternate approaches give better performance, consume less area, or draw less power. In recent EEMBC benchmarks, Tensilica proved that custom instructions can boost processor performance from 5x to 25x or even higher. (see www.tensilica.com/html/eembc_optimized.html for details).

"We believe that this new high-level, abstract instruction definition capability will accelerate the rapidly growing exchange of application solutions between Xtensa users within larger companies, and between our third party solutions providers and our customer base," added Rosenthal. "As more and more functional solutions – such as video and audio codecs, security processing and protocol processing – have been developed and are reused, our customers explore many different combinations of home-grown and third-party TIE extensions. The availability of abstract TIE plus the new Xtensa Xplorer IDE makes it easier for our customers to evaluate the combinations."

The Xtensa Processor Generator automatically creates a customized version of the Xtensa processor with the new designer-defined instructions in approximately one hour . The Xtensa Processor Generator accepts a new processor specification, including designer-defined instructions described in the TIE language, and automatically builds a correct-by-construction RTL (register-transfer level) description of the modified Xtensa processor that includes all the newly described functions and resources, as well as a complete matching software tool suite.

Pricing and Availability

The new higher-level TIE capabilities will be available to all Xtensa V licensees in the third quarter of 2003 at no additional charge.

About Tensilica

Tensilica was founded in July 1997 to address the growing need for optimized, application-specific microprocessor solutions in high-volume embedded applications. With a configurable and extensible microprocessor core called Xtensa, Tensilica is the only company that has automated and patented the time-consuming process of generating a customized microprocessor core along with a complete software development tool environment, producing new configurations in a matter of hours. For more information, visit www.tensilica.com.

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Editors' Notes:

• "Tensilica" and "Xtensa" are registered trademarks belonging to Tensilica Inc. All other trademarks are the property of their respective holders.

• Tensilica's announced licensees are Agilent, Astute Networks, Avision, Bay Microsystems, Berkeley Wireless Research Center, Broadcom, Cisco Systems, Conexant Systems, Cypress, ETRI, FUJIFILM Microdevices, Fujitsu Ltd., Hudson Soft, Hughes Network Systems, IC4IC, Ikanos Communications, JNI Corporation, Marvell, Mindspeed Technologies, National Semiconductor, NEC Networks, NEC Solutions, Nippon Telephone and Telegraph (NTT), Olympus Optical Co. Ltd., ONEX Communications, OptiX Networks, Osaka & Kyoto Universities, S2io, Sony, TranSwitch Corporation, Trebia Networks, Victor Company of Japan (JVC) and ZiLOG.