Tharas delivers Hammer 100, the Industry’s most advanced Accelerated Functional Verification System

SANTA CLARA, Calif. — May 10, 2004 — Tharas Systems, Inc., today announced Hammer(R) 100, the EDA industry's most advanced hardware-assisted simulation accelerator for functional verification of complex ASIC and system designs. Hammer 100 delivers industry-leading compilation speed, faster run-time performance, and an enhanced debug environment that offers ease-of-use and ease-of-adoption comparable to that of software simulators.

The patented Hammer custom-processor architecture compiles Verilog, VHDL or mixed-language designs at 20 to 50 million RTL gate equivalents per hour on a single workstation – the fastest compilation time in the industry. The modular compiler enables design changes without full compile for even faster design preparation time. Design blocks or chips can be compiled separately and linked later to allow for pre-compiled modules (PCM) that can be managed and linked during compile time. Only changed PCM is incrementally compiled and re-linked during source-level engineering change orders. Incremental compile can be performed on either the design or testbench source.

Hammer 100 now includes up to 4 gigabytes of memory to increase run-time performance up to two times faster than the earlier generation Hammer systems. The Hammer 100’s built-in arithmetic operators further speed commonly used computational functions in computing, graphics and DSP applications.

Advanced Trace Data Conversion for Debug Productivity

Debug of complex designs involves time-consuming process of converting gigabytes of trace data files into waveforms. The Hammer 100 now offers an advanced debug facility in concurrent, parallel and progressive waveform conversion to industry standard formats such as fast signal database (FSDB), value change dump (VCD), or VCD post-processing data (VPD).

Hammer 100’s concurrent waveform conversion capability offers dramatic reduction in time-to-waveforms, by compressing trace data and concurrently converting trace data to waveforms. Designers can start debug with the portion of the waveforms with all signals while more waveforms are being generated as accelerated verification proceeds. Parallel waveform capability allows conversion of compressed simulation trace data dumps across a network of workstations in parallel. Progressive Waveform Converter can be used during active debug sessions, allowing a verification engineer to save relevant trace data only if and when simulation fails or does not meet expected results. The user may choose to save signals for a certain number of clock cycles or trace data sets at the time simulation failed, walking backwards.

Enhanced language support expands ease-of-adoption

Hammer 100 environment is now compliant with IEEE 1364-2001 and IEEE 1076-2002. It accelerates a broad set of HDL constructs including latches, multiple clocks, gated clocks, switch-level models, models with signal strengths and user-defined primitives. All synthesizable HDL constructs are acceleratable, including memory models. Behavioral constructs, such as system tasks, user tasks and initial blocks, which are typically deployed in testbenches, can also be accelerated. In addition, Hammer 100 now supports delay elements, to facilitate designs using intellectual property or legacy blocks as is.

Hammer 100 HCS Compiler now supports either 32 or 64 bit Solaris and Linux workstations. Cross platform compilation capability allows design compilation on a Linux workstation while running the accelerated simulation on a Hammer system attached to a Solaris host or vice versa.

"Today's designs require engineers to consider a scalable verification platform that offers language compliance and debug productivity of a software simulator, and at the same time, the blazing speeds of a hardware assisted verification solution. Hammer 100 fulfills all of these key target requirements," said Rahm Shastry, president and CEO for Tharas. "Hammer 100 delivers an affordable platform with fast design turns and high debug productivity, all in an easy-to-adopt platform."

Pricing and Product Availability

Hammer 100 system pricing depends on user configuration. The list price starts at $150,000 for a 2 Million Gates configuration. Hammer 100 is available for production use immediately and supports Solaris and Linux platforms. Hammer 100 will also be available through a flexible rental program. For more information on product pricing and availability call Tharas in North America at 408.855.3200. For pricing and availability outside of North America visit http://www.tharas.com/contact.

About Tharas Systems

Founded in 1998, Tharas Systems is privately held with corporate headquarter located at 2518 Mission College Blvd., Suite 101, Santa Clara, CA 95054. Its high-performance verification technology leads to significant shortening of the verification cycle and material reduction in time-to-market for designers of complex integrated circuits and electronic systems. Tharas's Hammer custom-processor based hardware-assisted verification solution works in conjunction with popular Verilog and VHDL-based software simulators from Synopsys, Cadence Design, and Mentor Graphics.

Hammer is a trademark of Tharas Systems Inc. Tharas acknowledges trademarks or registered trademarks of other organizations for their respective products and services.

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WHAT CUSTOMERS ARE SAYING ABOUT HAMMER 100

"Our customers demand that we deliver increasingly complex and high performance Graphics Processing Units in less time and lower cost. Over the past few months, we have deployed Hammer 100 on our next generation GPU and have seen double-digit performance, better debug capability without compromising ease-of-use. We are deploying Hammer solution on multiple applications – RTL regression, gate-level acceleration, accelerated DFT and BIST." - Narendra Konda, Verification Manager, NVIDIA Corporation

"Tharas’ latest generation Hammer 100 solution is part of Sun's verification methodology to accelerate critical simulation jobs and helps microprocessor designer and verification engineers in reducing the runtime of their RTL and gate-level simulations." - Shrenik Mehta, Director, Frontend Technologies, Throughput Systems Sun Microsystems, Inc.