Mentor Graphics and Altera Unveil Strategy to Speed Industry Move to Systems-on-a-Programmable Chip

SAN FRANCISCO--(BUSINESS WIRE)--April 10, 2001--At the Embedded Systems Conference today, Mentor Graphics Corp. (Nasdaq:MENT) and Altera Corporation (Nasdaq:ALTR) unveiled a strategy to deliver a complete ``front-to-back'' design methodology for customers using Altera's Excalibur(TM) system-on-a-programmable-chip (SOPC) technology.

Excalibur solutions feature the implementation of embedded processors that were previously only available with traditional Application Specific Integrated Circuit (ASIC) design methodology. Mentor Graphics® and Altera will strengthen their technology alliance to provide complete solutions to enhance this new design flow.

The first solution in this initiative is the introduction of customized co-verification processor support packages (PSPs) for Altera's ARM®-based Excalibur embedded processor solutions. The custom PSP is based on the cycle-accurate PSPs for ARM-based Excalibur solutions already available in Mentor's Seamless® Co-Verification Environment (CVE(TM)) model library. With Seamless CVE and the PSPs for ARM-based Excalibur solutions, Altera customers can verify the embedded cores within Excalibur devices and the external interfaces to off-chip components during their design and debug phases, shortening overall design cycles by increasing the chance of first pass success.

The complete design solution will include Electronic Design Automation (EDA) tools for design capture, simulation, hardware/software co-verification, embedded software, physical synthesis, board-level signal integrity and C-based high-level design, in addition to embedded intellectual property (IP) MegaCore® logic functions. These new tools will provide early visibility into the design and verification process and will enable design teams to make tradeoffs throughout the design cycle that will increase their ability to reach time-to-market, performance and feature requirements.

``As more customers make the transition to SOPC solutions, it is critical that we provide them with a design methodology that enables new generations of products,'' said John Daane, Altera's chief executive officer. ``Extending our partnership with Mentor Graphics confirms our commitment to our customers that we deliver the Altera Advantage(TM) by offering them complete best-in-class technology.''

``Both Mentor and Altera recognize that for our mutual customers to develop applications based on SOPC architectures, new, easy-to-use, high-performance tools, specifically designed for PLD design flows, will be required,'' said Dr. Walden C. Rhines, chairman and chief executive officer for Mentor Graphics. ``This alliance will leverage our extensive technology portfolio, including Seamless CVE, ModelSim® and LeonardoSpectrum(TM), to deliver complete design flows for the new generation of Altera SOPC architectures.''

The new availability of co-verification support adds to recent Altera Excalibur solutions support announcements from Mentor Graphics. On March 12, 2001, Mentor Graphics and Altera announced support for the STAMP timing file format, allowing PLD and printed circuit board (PCB) designers to easily share PLD timing data for efficient board-level timing analysis.

In addition, Altera already has OEM agreements with Mentor Graphics for its LeonardoSpectrum synthesis and ModelSim simulation tools. Altera has integrated both tools into its Quartus(TM) II and MAX+PLUS® II development environments, and offers these to customers as part of its standard annual subscription agreement.

Design Flow Roadmap Addresses Wide Range of SOPC Design Needs

Mentor Graphics plans additional tool availability for the Excalibur solutions in the upcoming months that encompass multi-million gate design, IP-based development, embedded processor cores and high-level system design. The roadmap will include C-based system level design, embedded software development tools, additional IP core availability and will provide for tight integration with Altera SOPC development tools. Altera currently licenses twenty Inventra cores as part of its Altera Megafunction Partner Program (AMPPSM).

About Altera's Excalibur Embedded Processor Solutions

Combining logic, memory, and a processor core, Altera's new Excalibur embedded processor solutions allow engineers to integrate an entire system on a single PLD. The three families -- the Nios(TM) soft core embedded processor, the ARM-based hard core embedded processor, and the MIPS®-based hard core embedded processor -- offer the flexibility of processor cores with the integration of RAM and programmable logic.

Excalibur embedded processor solutions can be used in any application requiring processors and PLDs with gate counts up to 1,000,000 gates. They offer full integration with Altera's APEX(TM) PLD architecture, and are supported by the Quartus II development tool, which is optimized for the Excalibur embedded processor families.

Both Altera and Mentor Graphics will be exhibiting at the Embedded Systems Conference at the Moscone Center in San Francisco on April 9-13 at the Moscone Center.

About Altera Corporation

Altera Corporation, The Programmable Solutions Company®, was founded in 1983 and is a leading supplier of programmable logic devices (PLDs). Altera's CMOS-based PLDs are user-programmable semiconductor chips that enhance flexibility and reduce time-to-market for companies in the communications, computer peripheral, and industrial markets. By using high performance devices, software development tools, and sophisticated intellectual property cores, system-on-a-programmable-chip (SOPC) solutions can be created with embedded processors, memory, and other complex logic together on a single PLD. Altera common stock is traded on The Nasdaq Stock Market under the symbol ALTR. More information on Altera is available on the Internet at: http://www.altera.com.

About Mentor Graphics

Mentor Graphics Corporation (Nasdaq:MENT) is a world leader in electronic hardware and software design solutions, providing products and consulting services for the world's largest electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of nearly $600 million and employs approximately 2,750 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Ore. 97070-7777. Silicon Valley headquarters are located at 1001 Ridder Park Drive, San Jose, Calif. 95131-2314. World Wide Web site: www.mentor.com.

Mentor Graphics, XRAY, Seamless and Modelsim are registered trademarks of Mentor Graphics Corporation. Co-Verification Environment (CVE) is a trademark of Mentor Graphics Corporation. Calibre and xCalibre are also registered trademarks of Mentor Graphics Corporation.

Altera, The Programmable Solutions Company, Excalibur, Nios, Quartus, MegaCore, The Altera Advantage, Quartus, MAX+ PLUS, AMPP, APEX and specific device designations are trademarks and/or service marks of Altera Corporation in the U.S. and other countries.

ARM is a registered trademark of ARM Limited.

MIPS is a registered trademark of MIPS Technologies, Inc.

All other trademarks are the property of their respective holders.

Contact:

     Mentor Graphics       Amy Malagamba, 503/685-7836       amy_malagamba@mentor.com       or       Altera       Anna del Rosario, 408/544-7496       adelrosa@altera.com       or       Benjamin Group/BSMG Worldwide (Media)       Jeremiah Glodoveza, 415/352-2628 ext. 559       jeremiah@benjamingroup.com