Altera Delivers World's Most Versatile Embedded Processor with Nios II Family

Industry’s Leading Soft-Core Processor Delivers the Greatest Flexibility, Highest Performance, and Lowest Cost

San Jose, Calif., May 18, 2004 – Altera Corporation (NASDAQ: ALTR) today announced the immediate availability of the Nios^® II family of 32-bit RISC embedded processors. Altera’s second-generation soft-core embedded processor delivers more than 200 DMIPS in performance and can cost as little as 35 cents to implement in Altera’s FPGAs. Because the Nios II processor is a soft core, developers can choose from an unlimited combination of system configurations to meet their performance and cost targets without having to consider an ASIC for their system-level designs.

“Altera's Nios processors and Stratix FPGAs are at the very heart of our Maestro platform, delivering the core functionality that enables it to provide unprecedented data center functionality,” said Steve Elston, president-Americas, Crescendo Networks.  “We have been evaluating the Nios II processor for some time, and even in its pre-released form, it is a very impressive offering, providing 2X the performance in our product and considerable resource savings.  We plan to integrate Nios II processors into Maestro as soon as possible, as well as Stratix II FPGAs, both of which will boost Maestro’s processing speed and extend our performance advantage even further.”

The Ultimate in Flexibility

The Nios II family consists of three soft CPU cores; one for maximum system performance, one optimized for minimum logic usage, and one that strikes a balance between the two. All cores are 100 percent code compatible, letting designers change CPUs as their system requirements change without impacting their existing software investment. Building on the success of the previous generation, the Nios II family provides significantly higher performance with a fraction of the resources. Additionally, the Nios II processor features a robust software development suite that includes a compiler, integrated development environment (IDE), JTAG debugger, real-time operating system (RTOS), and TCP/IP stack.

Combined with Altera’s low-cost Cyclone™ series and high-performance Stratix^® series of FPGAs, and HardCopy™ structured ASIC family, the Nios II embedded  processor offers unmatched flexibility in price, performance, and features.

“With mainstream performance, reduced logic footprint, and robust development tools, the Nios II processor can be used in a broader range of embedded systems applications then even the first generation Nios processor,” said Tim Allen, Altera’s senior director of embedded processor development. “The adaptability, flexibility, and performance of our FPGAs combined with the capabilities of the Nios II processor will further differentiate Altera from any number of competing embedded solutions. With the first-generation Nios processor already in the hands of thousands of designers around the world, the Nios II family promises to be a driving force behind more FPGAs going into embedded systems.”

Allen will present architectural details of the Nios II embedded processor on Wednesday at the Embedded Processor Forum in San Jose.  For more information, please visit www.altera.com.

Features and Development Tool Support

• Nios II IDE  – Based on the open-source Eclipse project, the Nios II IDE provides a robust, graphical IDE / debugger environment that supports connection to the target hardware over JTAG, the Nios II instruction set simulator, and the ModelSim® hardware simulation tool from Mentor Graphics. Using Nios II IDE, developers can edit, compile, download, debug, and program on-board flash from a single, integrated development tool.
  
  
• MicroC/OS-II RTOS – The MicroC/OS-II RTOS is a royalty-free, source-available operating system from Micrium that supports the demanding requirements of RTCA DO-178B standard for avionic equipment.
  
  
• IP TCP/IP stack – The Lightweight IP TCP/IP stack provides a Berkeley sockets API supporting Internet protocol (IP), Internet control message protocol (ICMP), user datagram protocol (UDP), and transmission control protocol (TCP) with congestion control, RTT estimation, and fast recovery/fast retransmit.
  
  
• Custom Instructions – Unlike off-the-shelf MCU and competitive FPGA processor solutions, Nios II processor allows developers to extend the instruction set by adding up to 256 user-defined instructions to accelerate time-critical processing tasks.
  
  
• Peripherals – The Nios II processor is supported by over 60 peripherals, providing unrivaled configuration choices, including Ethernet, USB, memory controllers, etc. The SOPC Builder design tool featured in Altera’s Quartus® II development software supports all 60 peripherals and provides a wizard-based import tool designers can use in integrate their own custom logic functions.

Pricing and Availability

Nios development kits featuring Altera’s Stratix and Cyclone FPGAs can be ordered immediately with the Nios II family of processors and development tools. Customers with an active Nios subscription will automatically receive the Nios II processor and Nios II IDE upgrade.

About Altera

Altera Corporation (NASDAQ: ALTR) is the world’s pioneer in system-on-a-programmable-chip (SOPC) solutions. Combining programmable logic technology with software tools, intellectual property, and technical services, Altera provides high-value programmable solutions to approximately 14,000 customers worldwide.  More information is available at www.altera.com.

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