NEC Corporation Selects Avant!'s Nova-ExploreRTL to Automate Design Reuse Guidelines

Avant!'s Nova-ExploreRTL to Enhance Productivity of NEC's System LSI Design Environment

FREMONT, Calif., March 20 /PRNewswire/ -- Avant! Corporation (Nasdaq: AVNT) today announced that NEC Corporation (Nasdaq: NIPNY) has selected Nova-ExploreRTL design analyzer for its System LSI design environment. NEC's selection of Nova-ExploreRTL affirms Avant!'s leadership in the RTL design analysis market. NEC demonstrated Nova-ExploreRTL at the EDS Fair held February 1-2, 2001.

"NEC adopted Avant!'s RTL design analysis tool, Nova-ExploreRTL, to meet its requirements for increasing design complexity with shorter development cycles," said Nobuyuki Nishiguchi, department manager, System LSI Design Engineering Division, System LSI Operations Unit, NEC Electron Devices.

"Nova-ExploreRTL allows us to purify and verify the HDL code at the RTL level before the logic synthesis and simulation design phases by using both built-in design rules and additional rules that we have customized," continued Nishiguchi. "As a result, design bugs and iterations are reduced.

Nova-ExploreRTL simplifies creation of high quality, purified HDL IP, enabling both design reuse and a shorter development period."

"In addition," said Nishiguchi, "I think that Nova-ExploreRTL is an indispensable tool to promote reuse of HDL IP, because the reuse of such IP both outside and inside the company will become necessary in the future."

"We are pleased that NEC Corporation has chosen Nova-ExploreRTL for their System LSI design environment," said Gerald C. Hsu, chairman, CEO, and president of Avant! Corporation. "Nova-ExploreRTL's industry-leading solution to check RTL design guidelines and verify compliance with IP reuse guidelines will allow NEC and its customers to shorten design cycle times and improve product quality."

Nova-ExploreRTL
Nova-ExploreRTL analyzes the coding, clocking, DFT conformance, and reusability of RTL designs. If used prior to logic synthesis and simulation, Nova-ExploreRTL can detect 50% or more of the design errors at the RTL level, so that it is possible to go from RTL to the gate level of a design in a single pass. High-quality HDL code in conformance with IEEE and RMM standards is obtained. Also, using customized rules, customers can enforce their specific design styles and standards. Using Nova-ExploreRTL, detection of difficult coding errors, which previously could take several months, can be reduced to a few minutes. Since the checks are performed quickly and early in the design cycle, the designer can generate high-quality and reusable RTL code while greatly reducing development costs. Moreover, companies can quickly make and add new rules and guidelines. Nova-ExploreRTL has Verilog and VHDL versions with both batch and an easy to use GUI. Nova-ExploreRTL eliminates simulation and synthesis runs, shortening the design cycle time and reducing development costs.

About Avant!
Avant! Corporation develops, markets, and supports integrated circuit (IC) design automation software solutions (from system definition to mask synthesis) for the rapid design of multimillion gate products including system on chip (SoC). These ICs power the consumer electronics, Internet infrastructure, wireless, telecommunications, and automotive products. The Company is the leading provider of physical foundation IP libraries for IC design and provides a full suite of software for integrated circuit design, process simulation, device modeling, and mask synthesis.

Avant! is a global company with over 65 offices in 18 countries. Telephone: 510-413-8000. Fax: 510-413-8080. Worldwide web: www.avanticorp.com.

NOTE: Avant!, and Nova-ExploreRTL are trademarks of Avant! Corporation. All other company and product names mentioned herein are trademarks or registered trademarks of their respective owners and should be treated as such.

CONTACT: Clayton Parker, Head of Corporate Marketing of Avant! Corporation, 510-413-8011, or clayton_parker@avanticorp.com