MIPS-Based Products at Fall Processor Forum Raise the Bar on Next-Generation Embedded Systems

Broadcom, Cavium and PMC-Sierra Announce Designs for Networking and Communications Applications That Increase Performance, Lower Power and Reduce System Cost

MOUNTAIN VIEW, Calif., Oct. 7, 2004 - Some of the most innovative embedded processors unveiled earlier this week at Fall Processor Forum (FPF) are based on the MIPS® architecture, MIPS Technologies, Inc. (Nasdaq: MIPS) announced today. Offering significantly higher performance, greater power efficiency, and lower system cost, they include products from leading semiconductor licensees of MIPS Technologies and from the company itself.

FPF, a conference that combines the former Microprocessor and Embedded Processor Forums, is one of the largest annual technology events addressing new processor-related technologies. Broadcom Corp., Cavium Networks and PMC-Sierra, Inc. made news at this year's event by taking advantage of MIPS Technologies' open, flexible business model, industry-standard architecture, and vast ecosystem of optimized software to develop leading-edge, multiple-core processors for next-generation networking and communications applications.

Broadcom
Broadcom's latest family of 64-bit MIPS-Based™ processors includes the industry's first gigahertz quad-core broadband processor, which delivers up to 10,000 Dhrystone MIPS, 100 Gbps memory bandwidth, and 145 Gpbs I/O bandwidth in a low-power, single-chip solution. Integrating multiple MIPS-Based CPU cores onto a single chip achieves much higher aggregate performance compared to the use of multiple discrete cores, while dramatically reducing board space and power dissipation. Broadcom's new dual- and quad-core processors are targeted at data networking and communications applications, as well as security, storage, 3G wireless infrastructure, and high-density computing applications.

Cavium Networks
Cavium Networks introduced the industry's first single-chip Network Services Processor (NSP) family, which uses as many as 16 MIPS64®-based cnMIPS™ cores for Internet services, content and security processing. According to the company, OCTEON™ NSPs deliver integrated application performance of up to 10 Gbps, with as much as a 5x benefit in cost, performance and power over existing solutions. Today's implementations of higher layer applications processing require a myriad of chips, including control-plane processors, data-plane processors and coprocessors for Internet services and security. But OCTEON NSPs introduce a revolutionary new SOC architecture that integrates the functionality of these various types of processors onto a single chip.

PMC-Sierra
PMC-Sierra's latest 64-bit MIPS-Powered™ multiprocessor is the 1.8 GHz, dual-CPU RM11200™. The highly integrated multiprocessor matches up two newly designed 1.8 GHz E11K™ CPU cores with multiple high-speed memory and I/O interfaces, including dual DDR2, dual PCI Express™, quad Gigabit Ethernet ports, and HyperTransport™, to address the high bandwidth requirements for next-generation networking, storage and communications equipment. The RM11200 was designed to give customers the highest level of processing performance, low power and leading-edge integration for applications such as enterprise routers, storage systems and DSLAMs.

PMC-Sierra also announced its Open Source Network Computing (NC) initiative to enable rapid commercialization of low-power thin client solutions for education, enterprise, self-service kiosks, retail displays, Internet cafes and advanced video-on-demand. The company's open source NC solution, the PMC Xiao Hu™, is a commercially available single-board thin client solution co-developed with China's Tsinghua University, MIPS Technologies and ATI Technologies, Inc. Compared to the traditional desktop PC approach, the combination of the PMC Xiao Hu board with Linux software and a MIPS-Powered™ processor reduces power by over 90 percent and IT costs by 70 percent.

MIPS Technologies
MIPS Technologies also made news at FPF with the launch of the DSP application-specific extension (ASE) to the MIPS architecture, which improves signal processing performance up to 300 percent over a range of embedded applications. Supported by a complete suite of software development tools and the MIPS DSP Library, the DSP ASE enables SOC designers to simplify their design environment and lower system cost by eliminating hardwired logic and migrating DSP functionality onto a MIPS-Based™ host processor. DVD recorders, digital cameras, residential gateways and VoIP phones are examples of the growing list of consumer products that require an increasing amount of signal and media processing horsepower. In the cost-sensitive, high-volume consumer electronics market, eliminating unnecessary hardware and tool chains and reducing royalty payments can result in savings of millions of dollars.

About MIPS Technologies
MIPS Technologies, Inc. is a leading provider of industry-standard processor architectures and cores for digital consumer and business applications. The company drives the broadest architectural alliance that is delivering 32- and 64-bit embedded RISC solutions. The company licenses its intellectual property to semiconductor companies, ASIC developers and system OEMs. MIPS Technologies and its licensees offer the widest range of robust, scalable processors in standard, custom, semi-custom and application-specific products. The company is based in Mountain View, Calif., and can be reached at +1 (650) 567-5000 or www.mips.com.

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