Prosilog releases Magillem V2.2 with Spirit 1.0 IP packaging capabilities

Cergy, France – January 10, 2005 – Prosilog SA, a leading provider of innovative solutions for SoC design and verification, announces the new release 2.2 of its Magillem platform based design tool. This release includes the “SPIRIT Editor” module which allows the packaging of IP blocks according to the SPIRIT* 1.0 specification, released on December 8th, 2004. (http://www.spiritconsortium.com/)
 
Prosilog is committed to provide the electronic community with solutions that facilitate the IP integration and reuse. With this Magillem 2.2 release, designers are able to import and instantiate their IP SPIRIT compatible blocks in Magillem. Then, after the construction of the platform, the design netlist can be exported either in VHDL/Verilog languages or in the SPIRIT format.  
 
“ We are pleased with the traction that SPIRIT has gained in the market with the delivery of the version 1.0 specification”, says Ralph von Vignau, SPIRIT Chairman and Director Technology and Standards of Philips Semiconductors' Chief Technology Office - ReUse Technology Group. Companies such as Prosilog, are delivering SPIRIT-compliant EDA tools, demonstrating that an ecosystem focused on an open standard for IP reuse is building rapidly. “
 
“Being an early supporter of the SPIRIT initiative, we have been reviewing actively for the last months the SPIRIT 1.0 RTL standard, says Philippe Laharrague, VP Sales & Marketing at Prosilog. We are now extending our contribution to participate into the new ESLTechnical Working Group for the upcoming SPIRIT 2.0 release.”
 
About Prosilog SA

Prosilog SA is developing innovative RTL & System Level Design EDA tools, as well as soft IP cores, which help SoC designers to reduce the cycle time of their product design.
Prosilog SA provides solutions aiming at automating some of the conception and verification phases of SoC design.
 
The Prosilog’s environment for specifying, verifying and implementing complex SoC’s, handles system descriptions both at transactional and RTL levels and therefore, facilitates the SoC early architecture exploration phase.
Its graphical front-end, allows the easy integration of different IP blocks, the automatic interface and interconnect generation between IP's as well as the insertion of verification modules.
The IP Creator module enables the fast generation of a VCI, or OCP interface, making it easy to create a common interface for any IP portfolio. The powerful translators SystemC/HDL and HDL/SystemC offer the necessary connection between both SystemC and HDL worlds. www.prosilog.com
 
(*) SPIRIT : Structure for Packaging, Integrating and Re-using IP within Tool flows

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